HD6417144 RENESAS [Renesas Technology Corp], HD6417144 Datasheet - Page 227

• Manufacturer Part Number: HD6417144
• Description: 32-Bit RISC Microcomputer SuperHTM RISC engine Family/SH7144 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

On-Chip Peripheral Module Request Mode: In this mode a transfer is performed at the transfer
request signal (interrupt request signal) of an on-chip peripheral module. As indicated in table
10.3, there are ten transfer request signals: five from the multifunction timer pulse unit (MTU),
which are compare match or input capture interrupts; the receive data full interrupts (RXI) and
transmit data empty interrupts (TXI) of the two serial communication interfaces (SCI); and the
A/D conversion end interrupt (ADI1) of the A/D converter. When DMA transfers are enabled (DE
= 1, DME = 1, TE = 0, NMIF = 0, AE = 0), a transfer is performed upon the input of a transfer
request signal.
The transfer request source need not be the data transfer source or transfer destination. However,
when the transfer request is set by RXI (transfer request because SCI’s receive data is full), the
transfer source must be the SCI’s receive data register (RDR). When the transfer request is set by
TXI (transfer request because SCI’s transmit data is empty), the transfer destination must be the
SCI’s transmit data register (TDR). Also, if the transfer request is set to the A/D converter, the
data transfer destination must be the A/D converter register.
Table 10.3 Selecting On-Chip Peripheral Module Request Modes with RS Bits
Notes: MTU: Multifunction timer pulse unit.
RS3 RS2 RS1 RS0
0
0
1
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
SCI0, SCI1: Serial communications interface channels 0 and 1.
ADDR1: A/D converter’s A/D register.
TDR_0, TDR_1: SCI_0 and SCI_1 transmit data registers.
RDR_0, RDR_1: SCI_0 and SCI_1 receive data registers.
*
External memory, memory-mapped external device, on-chip memory, and on-chip
peripheral module (excluding DMAC, DTC, BSC, and UBC).
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
DMAC Transfer
Request Source
MTU
MTU
MTU
MTU
MTU
A/D1
SCI0 transmit block TXI_0
SCI0 receiver block RXI_0
SCI1 transmit block TXI_1
SCI1 receiver block RXI_1
DMA Transfer
Request Signal Source
TGIA_0
TGIA_1
TGIA_2
TGIA_3
TGIA_4
ADI1
10. Direct Memory Access Controller (DMAC)
Rev.4.00 Mar. 27, 2008 Page 183 of 882
Any*
Any*
Any*
Any*
Any*
ADDR1 Any*
Any*
RDR0
Any*
RDR1
Desti-
nation Bus Mode
Any*
Any*
Any*
Any*
Any*
TDR0
Any*
TDR1
Any*
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