HD6417144 RENESAS [Renesas Technology Corp], HD6417144 Datasheet - Page 89

• Manufacturer Part Number: HD6417144
• Description: 32-Bit RISC Microcomputer SuperHTM RISC engine Family/SH7144 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

2.6
2.6.1
The CPU has five processing states: reset, exception processing, bus release, program execution
and power-down. Figure 2.4 shows the transitions between the states.
When an internal power-on
reset by WDT or internal manual reset by
WDT occurs
Interrupt sources generated
or DMAC/DTC address
error occurs*
Note:
*
Enabled only in masked ROM version and ROM less version. Disabled in F-ZTAT version and emulator.
Processing States
State Transitions
Bus request
generated
Bus release state
From any state
when RES = 0
Figure 2.4 Transitions between Processing States
Sleep mode
Bus request
cleared
Bus request
cleared
Power-on reset state
Bus request
generated
Bus request
generated
Bus request
cleared
SSBY bit cleared
for SLEEP
instruction
processing
Exception
Program execution state
source
occurs
processing state
RES = 1
From any state when
RES = 1, MRES = 0,
Exception
RES = 0
Exception
processing
ends
Rev.4.00 Mar. 27, 2008 Page 45 of 882
RES = 1,
MRES = 1
Manual reset state
Software standby mode
SSBY bit set
for SLEEP
instruction
REJ09B0108-0400
Reset state
Power-down state
NMI or IRQ interrupt
source occurs
2. CPU