HD6417144 RENESAS [Renesas Technology Corp], HD6417144 Datasheet - Page 268

• Manufacturer Part Number: HD6417144
• Description: 32-Bit RISC Microcomputer SuperHTM RISC engine Family/SH7144 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

11.
11.3.2
The TMDR registers are 8-bit readable/writable registers that are used to set the operating mode of
each channel. The MTU has five TMDR registers, one for each channel. TMDR register settings
should be changed only when TCNT operation is stopped.
Rev.4.00 Mar. 27, 2008 Page 224 of 882
REJ09B0108-0400
Bit
7, 6
5
4
3
2
1
0
Multi-Function Timer Pulse Unit (MTU)
Bit Name
—
BFB
BFA
MD3
MD2
MD1
MD0
Timer Mode Register (TMDR)
All 1
0
0
Initial Value
0
0
0
0
R/W
—
R/W
R/W
R/W
R/W
R/W
R/W
Description
Reserved
These bits are always read as 1. The write value
should always be 1.
Buffer Operation B
Specifies whether TGRB is to operate in the normal
way, or TGRB and TGRD are to be used together for
buffer operation. When TGRD is used as a buffer
register, TGRD input capture/output compare is not
generated.
In channels 1 and 2, which have no TGRD, bit 5 is
reserved. It is always read as 0 and cannot be
modified.
0: TGRB and TGRD operate normally
1: TGRB and TGRD used together for buffer
Buffer Operation A
Specifies whether TGRA is to operate in the normal
way, or TGRA and TGRC are to be used together for
buffer operation. When TGRC is used as a buffer
register, TGRC input capture/output compare is not
generated.
In channels 1 and 2, which have no TGRC, bit 4 is
reserved. It is always read as 0 and cannot be
modified.
0: TGRA and TGRC operate normally
1: TGRA and TGRC used together for buffer
Modes 0 to 3
These bits are used to set the timer operating mode.
See table 11.9 for details.
operation
operation