HD6417144 RENESAS [Renesas Technology Corp], HD6417144 Datasheet - Page 483
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HD6417144
Manufacturer Part Number
HD6417144
Description
32-Bit RISC Microcomputer SuperHTM RISC engine Family/SH7144 Series
Manufacturer
RENESAS [Renesas Technology Corp]
Datasheet
1.HD6417144.pdf
(930 pages)
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13.5.1
Figure 13.11 shows a sample flowchart for multiprocessor serial data transmission. For an ID
transmission cycle, set the MPBT bit in SSR to 1 before transmission. For a data transmission
cycle, clear the MPBT bit in SSR to 0 before transmission. All other SCI operations are the same
as those in asynchronous mode.
Multiprocessor Serial Data Transmission
Figure 13.11 Sample Multiprocessor Serial Transmission Flowchart
Write transmit data to TDR and
as an output port with the PFC
Clear TE bit in SCR to 0;
Read TDRE flag in SSR
Read TEND flag in SSR
set MPBT bit in SSR
Clear TDRE flag to 0
All data transmitted?
Start transmission
select the TxD pin
Break output?
Clear DR to 0
Initialization
TDRE = 1
TEND = 1
<End>
Yes
Yes
Yes
Yes
No
No
No
No
[1]
[2]
[3]
[4]
[1] SCI initialization:
[2] SCI status check and transmit
[3] Serial transmission continuation
[4] Break output at the end of serial
13. Serial Communication Interface (SCI)
Rev.4.00 Mar. 27, 2008 Page 439 of 882
Set the TxD pin using the PFC.
After the TE bit is set to 1, a
frame period of 1s is output, and
transmission is enabled. This
action doesn't initiate immediate
data transmission.
data write:
Read SSR and check that the
TDRE flag is set to 1, then write
transmit data to TDR. Set the
MPBT bit in SSR to 0 or 1.
Finally, clear the TDRE flag to 0.
procedure:
To continue serial transmission,
be sure to read 1 from the TDRE
flag to confirm that writing is
possible, then write data to TDR,
and then clear the TDRE flag to
0. Checking and clearing of the
TDRE flag is automatic when the
DMAC or DTC is activated by a
transmit data empty interrupt
(TXI) request, and data is written
to TDR.
transmission:
To output a break in serial
transmission, first clear the port
data register (DR) to 0, then
clear the TE bit to 0 in SCR and
REJ09B0108-0400
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