HD6417144 RENESAS [Renesas Technology Corp], HD6417144 Datasheet - Page 432

• Manufacturer Part Number: HD6417144
• Description: 32-Bit RISC Microcomputer SuperHTM RISC engine Family/SH7144 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

12. Watchdog Timer
12.4.5
When TCNT overflows in watchdog timer mode, the WOVF bit of RSTCSR is set to 1 and a
WDTOVF signal is output. When the RSTE bit in RSTCSR is set to 1, TCNT overflow enables an
internal reset signal to be generated for the entire chip. Figure 12.5 shows this timing.
12.5
During interval timer mode operation, an overflow generates an interval timer interrupt (ITI). The
interval timer interrupt is requested whenever the OVF flag is set to 1 in TCSR. OVF must be
cleared to 0 in the interrupt handling routine.
Table 12.2 WDT Interrupt Source (in Interval Timer Mode)
Rev.4.00 Mar. 27, 2008 Page 388 of 882
REJ09B0108-0400
Name
ITI
Timing of Setting Watchdog Timer Overflow Flag (WOVF)
Interrupt Source
φ
Overflow signal
(internal signal)
WOVF
TCNT
Interrupt Source
TCNT overflow
Figure 12.5 Timing of Setting WOVF
H'FF
H'00
Interrupt Flag
OVF
DMAC/DTC Activation
Impossible