HD6417144 RENESAS [Renesas Technology Corp], HD6417144 Datasheet - Page 66

• Manufacturer Part Number: HD6417144
• Description: 32-Bit RISC Microcomputer SuperHTM RISC engine Family/SH7144 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

2. CPU
Table 2.3
Multiply/Multiply-and-Accumulate Operations: 16-bit × 16-bit → 32-bit multiply operations
are executed in one and two states. 16-bit × 16-bit + 64-bit → 64-bit multiply-and-accumulate
operations are executed in two and three states. 32-bit × 32-bit → 64-bit multiply and 32-bit × 32-
bit + 64-bit → 64-bit multiply-and-accumulate operations are executed in two to four states.
T Bit: The T bit in the status register changes according to the result of the comparison. Whether a
conditional branch is taken or not taken depends upon the T bit condition (true/false). The number
of instructions that change the T bit is kept to a minimum to improve the processing speed.
Table 2.4
Immediate Data: Byte (8-bit) immediate data is located in an instruction code. Word or longword
immediate data is not located in instruction codes but in a memory table. An immediate data
transfer instruction (MOV) accesses the memory table using the PC relative addressing mode with
displacement.
Rev.4.00 Mar. 27, 2008 Page 22 of 882
REJ09B0108-0400
CPU of This LSI
BRA
ADD
CPU of This LSI
CMP/GE
BT
BF
ADD
CMP/EQ
BT
TRGET
R1,R0
R1,R0
TRGET0
TRGET1
#−1,R0
#0,R0
TRGET
Delayed Branch Instructions
T Bit
Description
T bit is set when R0 ≥ R1. The
program branches to TRGET0
when R0 ≥ R1 and to TRGET1
when R0 < R1.
T bit is not changed by ADD.
T bit is set when R0 = 0. The
program branches if R0 = 0.
Description
Executes the ADD before
branching to TRGET.
Example of Conventional CPU
ADD.W
BRA
Example of Conventional CPU
CMP.W
BGE
BLT
SUB.W
BEQ
R1,R0
TRGET0
TRGET1
#1,R0
TRGET
R1,R0
TRGET