HD6417144 RENESAS [Renesas Technology Corp], HD6417144 Datasheet - Page 522

• Manufacturer Part Number: HD6417144
• Description: 32-Bit RISC Microcomputer SuperHTM RISC engine Family/SH7144 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

14. I
Rev.4.00 Mar. 27, 2008 Page 478 of 882
REJ09B0108-0400
Bit
5
4
2
Bit Name Initial Value R/W Description
MST
TRS
C Bus Interface (IIC) Option
0
0
R/W
R/W
Master/Slave Select
Transmission/Reception Select
00: Slave receive mode
01: Slave transmit mode
10: Master receive mode
11: Master transmit mode
Both MST and TRS bits will be cleared by hardware when
they lose in a bus contention in master mode of the I
format. The mode changes to slave receive mode. When
the I
transmission or reception is automatically selected by the
hardware, according to the setting of the R/ W bit of the first
frame after the start condition has been satisfied.
Even if an attempt is made to change the TRS bit during the
transfer of data, the change is suspended until transmission
of data has been completed; the bit is then changed.
[MST clearing conditions]
1. Writing of 0 to this bit by software
2. Lose in a bus contention in master mode of the I
[MST setting conditions]
1. Writing of 1 to this bit by software (MST clearing
2. Writing of 1 to this bit after reading MST = 0 (MST
[TRS clearing conditions]
1. Writing of 0 to this bit by software (except TRS setting
2. Writing of 0 to this bit after TRS = 1 is read (TRS setting
3. Lose in a bus contention in master mode of the I
[TRS setting conditions]
1. Writing of 1 to this bit by software (except TRS clearing
2. Writing of 1 to this bit after reading TRS = 0 (TRS
3. When 1 is received as the R/W bit of the first frame
format
condition 1)
clearing condition 2)
condition 3)
condition 3)
format
condition 3)
clearing condition 3)
address matched in the I
2
C bus format is used in the slave-receive mode,
2
C bus format in slave mode.
2
2
2
C bus
C bus
C bus