HD6417144 RENESAS [Renesas Technology Corp], HD6417144 Datasheet - Page 61

• Manufacturer Part Number: HD6417144
• Description: 32-Bit RISC Microcomputer SuperHTM RISC engine Family/SH7144 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

2.2.2
The control registers consist of three 32-bit registers: status register (SR), global base register
(GBR), and vector base register (VBR). The status register indicates processing states. The global
base register functions as a base address for the indirect GBR addressing mode to transfer data to
the registers of on-chip peripheral modules. The vector base register functions as the base address
of the exception processing vector area (including interrupts).
Status Register (SR):
Bit
31 to
10
9
8
Bit
7
6
5
4
3, 2
1
0
Bit Name
—
M
Q
Bit Name
I3
I2
I1
I0
—
S
T
Control Registers
Initial Value
All 0
Undefined
Undefined
Initial Value
1
1
1
1
All 0
Undefined
Undefined
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
Used by the DIV0U, DIV0S, and DIV1 instructions.
Used by the DIV0U, DIV0S, and DIV1 instructions.
Description
Interrupt mask bits.
Reserved
These bits are always read as 0. The write value
should always be 0.
S bit
Used by the MAC instruction.
T bit
The MOVT, CMP/cond, TAS, TST, BT (BT/S), BF
(BF/S), SETT, and CLRT instructions use the T bit to
indicate true (1) or false (0).
The ADDV, ADDC, SUBV, SUBC, DIV0U, DIV0S,
DIV1, NEGC, SHAR, SHAL, SHLR, SHLL, ROTR,
ROTL, ROTCR, and ROTCL instructions also use the
T bit to indicate carry/borrow or overflow/underflow.
Rev.4.00 Mar. 27, 2008 Page 17 of 882
REJ09B0108-0400
2. CPU