HD6417144 RENESAS [Renesas Technology Corp], HD6417144 Datasheet - Page 571

• Manufacturer Part Number: HD6417144
• Description: 32-Bit RISC Microcomputer SuperHTM RISC engine Family/SH7144 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Scope of Initialization:
The initialization executed by this function covers the following items:
• ICDRE and ICDRF internal flags
• Transmit/receive sequencer and internal operating clock counter
• Internal latches for retaining the output state of the SCL and SDA pins (wait, clock, data
The following items are not initialized:
• Actual register values (ICDR, SAR, SARX, ICMR, ICCR, ICSR, SCRX (except for the
• Internal latches used to retain register read information for setting/clearing flags in the ICMR,
• The value of the ICMR register bit counter (BC2 to BC0)
• Generated interrupt sources (interrupt sources transferred to the interrupt controller)
Notes on Initialization:
• Interrupt flags and interrupt sources are not cleared; therefore, flag clearing measures must be
• Basically, other register flags are not cleared either; therefore, flag clearing measures must be
• If a flag clearing setting is made during transmission/reception, the IIC module will stop
The value of the BBSY bit cannot be modified directly by this module clear function, but since pin
waveforms with stop condition may be generated depending on the state and release timing of the
SCL and SDA pins, causing the BBSY bit to be cleared. Similarly, switching of the state may
influence other bits and flags.
To prevent problems caused by these factors, the following procedure should be used when
initializing the IIC state.
1. Execute initialization of the internal state by clearing the ICE bit.
2. Execute a stop condition issue instruction (write 0 to BBSY and SCP) to clear the BBSY bit to
3. Re-execute initialization of the internal state by clearing the ICE bit.
4. Initialize (reset) the IIC registers.
output, etc.)
ICDRE and ICDRF flags)
ICCR, and ICSR registers
taken as necessary.
taken as necessary.
transmitting/receiving at that point and the SCL and SDA pins will be released. When
transmission/reception is started again, register initialization, etc., must be carried out as
necessary to enable correct communication as a system.
0, and wait for two transfer rate clock cycles.
Rev.4.00 Mar. 27, 2008 Page 527 of 882
14. I
2
C Bus Interface (IIC) Option
REJ09B0108-0400