HD6417144 RENESAS [Renesas Technology Corp], HD6417144 Datasheet - Page 723
HD6417144
Manufacturer Part Number
HD6417144
Description
32-Bit RISC Microcomputer SuperHTM RISC engine Family/SH7144 Series
Manufacturer
RENESAS [Renesas Technology Corp]
Datasheet
1.HD6417144.pdf
(930 pages)
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Notes: 1. Prewriting (setting erase block data to all 0s) is not necessary.
Increment address
2. Verify data is read in 32-bit (longword) units.
3. Make only a single-bit specification in the erase block register 1 (EBR1) and the erase block
4. Erasing is performed in block units. To erase multiple blocks, each block must be erased in turn.
register 2 (EBR2).
Figure 19.10 Erase/Erase-Verify Flowchart
No
No
Set block start address as verify address
H'FF dummy write to verify address
* 4
All erase block erased?
Set EBR1 and EBR2
Last address of block?
Verify data = all 1s?
Read verify data
Wait (t
End of erasing
SWE bit ← 1
Disable WDT
Enable WDT
ESU bit ← 1
ESU bit ← 0
SWE bit ← 0
Wait (t
Wait (t
Erase start
Wait (t
EV bit ← 1
Wait (t
Wait (t
E bit ← 1
Wait (t
E bit ← 0
EV bit ← 0
Wait (t
Wait (t
n ← 1
SSWE
CSWE
SESU
CESU
Yes
SEV
SEVR
SE
CE
CEV
) μs
Yes
)
Yes
)
)
)
)
)
)
)
* 1
No
* 3
* 2
Rev.4.00 Mar. 27, 2008 Page 679 of 882
19. Flash Memory (F-ZTAT Version)
SWE bit ← 0
Erase failure
EV bit ← 0
Wait (t
Wait (t
n ≤ 100?
CSWE
CEV
Yes
)
)
No
n ← n + 1
REJ09B0108-0400
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