HD6417144 RENESAS [Renesas Technology Corp], HD6417144 Datasheet - Page 154

• Manufacturer Part Number: HD6417144
• Description: 32-Bit RISC Microcomputer SuperHTM RISC engine Family/SH7144 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

7. User Break Controller (UBC)
Break on CPU Data Access Cycle
1. Register settings: UBARH = H'0012
2. Register settings: UBARH = H'00A8
Break on DMAC/DTC Cycle
1. Register settings: UBARH = H'0076
2. Register settings: UBARH = H'0023
Rev.4.00 Mar. 27, 2008 Page 110 of 882
REJ09B0108-0400
Conditions set:
A user break interrupt occurs when word data is written into address H'00123456.
Conditions set:
A user break interrupt does not occur because the word access was performed on an even
address.
Conditions set:
A user break interrupt occurs when longword data is read from address H'0076BCDC.
Conditions set:
A user break interrupt does not occur because no instruction fetch is performed in the
DMAC/DTC cycle.
Address: H'00123456
Address: H'00A80391
Address: H'002345C8
UBARL = H'3456
UBBR = H'006A
UBCR = H'0000
Bus cycle: CPU, data access, write, word
Interrupt requests enabled
UBARL = H'0391
UBBR = H'0066
UBCR = H'0000
Bus cycle: CPU, data access, read, word
Interrupt requests enabled
UBARL = H'BCDC
UBBR = H'00A7
UBCR = H'0000
Address: H'0076BCDC
Bus cycle: DMAC/DTC, data access, read, longword
Interrupt requests enabled
UBARL = H'45C8
UBBR = H'0094
UBCR = H'0000
Bus cycle: DMAC/DTC, instruction fetch, read
(operand size is not included in conditions)
Interrupt requests enabled