HD6417144 RENESAS [Renesas Technology Corp], HD6417144 Datasheet - Page 83

• Manufacturer Part Number: HD6417144
• Description: 32-Bit RISC Microcomputer SuperHTM RISC engine Family/SH7144 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Note:
Instruction
DT
EXTS.B
EXTS.W
EXTU.B
EXTU.W
MAC.L
MAC.W
MUL.L
MULS.W
MULU.W
NEG
NEGC
SUB
SUBC
SUBV
*
Rn
Rm,Rn
Rm,Rn
Rm,Rn
Rm,Rn
@Rm+,@Rn+ 0000nnnnmmmm1111
@Rm+,@Rn+ 0100nnnnmmmm1111
Rm,Rn
Rm,Rn
Rm,Rn
Rm,Rn
Rm,Rn
Rm,Rn
Rm,Rn
Rm,Rn
The normal number of execution states is shown. (The number in parentheses is the
number of states when there is contention with the preceding or following instructions.)
Instruction Code
0100nnnn00010000
0110nnnnmmmm1110
0110nnnnmmmm1111
0110nnnnmmmm1100
0110nnnnmmmm1101
0000nnnnmmmm0111
0010nnnnmmmm1111
0010nnnnmmmm1110
0110nnnnmmmm1011
0110nnnnmmmm1010
0011nnnnmmmm1000
0011nnnnmmmm1010
0011nnnnmmmm1011
Operation
Rn – 1 → Rn, when Rn
is 0, 1 → T. When Rn is
nonzero, 0 → T
Byte in Rm is sign-
extended → Rn
Word in Rm is sign-
extended → Rn
Byte in Rm is zero-
extended → Rn
Word in Rm is zero-
extended → Rn
Signed operation of
(Rn) × (Rm) + MAC →
MAC 32 × 32 + 64 →
64 bits
Signed operation of
(Rn) × (Rm) + MAC →
MAC 16 × 16 + 64 →
64 bits
Rn × Rm → MACL,
32 × 32 → 32 bits
Signed operation of
Rn × Rm → MACL 16 ×
16 → 32 bits
Unsigned operation of
Rn × Rm → MACL 16 ×
16 → 32 bits
0 – Rm → Rn
0 – Rm – T → Rn,
Borrow → T
Rn – Rm → Rn
Rn – Rm – T → Rn,
Borrow → T
Rn – Rm → Rn,
Underflow → T
Rev.4.00 Mar. 27, 2008 Page 39 of 882
Execution
States
1
1
1
1
1
3/(2 to 4)* —
3/(2)*
2 to 4*
1 to 3*
1 to 3*
1
1
1
1
1
REJ09B0108-0400
T Bit
Comparison
result
—
—
—
—
—
—
—
—
—
Borrow
—
Borrow
Overflow
2. CPU