HD6417144 RENESAS [Renesas Technology Corp], HD6417144 Datasheet - Page 543

• Manufacturer Part Number: HD6417144
• Description: 32-Bit RISC Microcomputer SuperHTM RISC engine Family/SH7144 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

11. Read the ACKB bit in ICSR.
12. Clear the IRIC flag to 0.
Note:
Data should not be
written to ICDR.
Confirm that the slave device returns acknowledgement (ACKB bit is 0). When there is still
data to be transmitted, go to step 9 to continue the next transmission. When the slave device
does not return acknowledgement (ACKB bit is set to 1), follow step 12 to end transmission.
Write 0 to the ACKE bit in ICCR, to clear the received ACKB bit to 0.
Write 0 to BBSY and SCP in ICCR. This changes SDA from low to high when SCL is high,
and generates the stop condition.
User processing
(Slave output)
(Master output)
(Master output)
Figure 14.8 An Example of the Timing of Operations in Master Transmit Mode
ICDRE
ICDRT
ICDRS
SDA
IRTR
IRIC
SDA
SCL
Start condition generation
(start condition issuance)
[4] Write 1 to BBSY
and 0 to SCP
generation
[5]
Interrupt
request
Address + R/W
Address + R/W
[6] ICDR write
bit 7
1
(MLS = WAIT = 0)
bit 6
2
bit 5
3
Slave address
bit 4
[6] IRIC clear
4
bit 3
5
Rev.4.00 Mar. 27, 2008 Page 499 of 882
bit 2
6
bit 1
14. I
7
R/W
bit 0
[9] ICDR write
2
8
C Bus Interface (IIC) Option
generation
[7]
A
Interrupt
request
9
REJ09B0108-0400
Data 1
Data 1
bit 7
[9] IRIC clear
1
Data 1
bit 6
2