HD6417144 RENESAS [Renesas Technology Corp], HD6417144 Datasheet - Page 140

• Manufacturer Part Number: HD6417144
• Description: 32-Bit RISC Microcomputer SuperHTM RISC engine Family/SH7144 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

6. Interrupt Controller (INTC)
6.7
Table 6.3 lists the interrupt response time, which is the time from the occurrence of an interrupt
request until the interrupt exception processing starts and fetching of the first instruction of the
interrupt service routine begins. Figure 6.5 shows an example of the pipeline operation when an
IRQ interrupt is accepted.
Table 6.3
Note: m1 to m4 are the number of states needed for the following memory accesses.
Rev.4.00 Mar. 27, 2008 Page 96 of 882
REJ09B0108-0400
Item
DMAC/DTC active
judgment
Interrupt priority judgment
and comparison with SR
mask bits
Wait for completion of
sequence currently being
executed by CPU
Time from start of interrupt
exception processing until
fetch of first instruction of
exception service routine
starts
Interrupt
response
time
m1: SR save (longword write)
m2: PC save (longword write)
m3: Vector address read (longword read)
m4: Fetch first instruction of interrupt service routine
* 0.38 to 0.40 µs at 50 MHz is the value in the case that m1 = m2 = m3 = m4 = 1.
Interrupt Response Time
Interrupt Response Time
Maximum: 12 + 2 (m1 + m2
Minimum: 10
Total: (7 or 8) + m1 +
NMI, Peripheral
Module
0 or 1
2
X (≥ 0)
5 + m1 + m2 + m3
m2 + m3+X
+ m3) + m4
Number of States
IRQ
1
3
X (≥ 0)
5 + m1 + m2 + m3
9 + m1 + m2 +
m3 + X
12
13 + 2 (m1 + m2
+ m3) + m4
Remarks
signals for which
DMAC/DTC activation is
possible
The longest sequence is for
interrupt or address-error
exception processing (X = 4
+ m1 + m2 + m3 + m4). If
an interrupt-masking
instruction follows, however,
the time may be even
longer.
Performs the saving PC and
SR, and vector address
fetch.
0.38 to 0.40 µs at 50 MHz*
1 state required for interrupt
0.20 to 0.24 µs at 50 MHz