HD6417144 RENESAS [Renesas Technology Corp], HD6417144 Datasheet - Page 40

• Manufacturer Part Number: HD6417144
• Description: 32-Bit RISC Microcomputer SuperHTM RISC engine Family/SH7144 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 8 Data Transfer Controller (DTC)
Table 8.1
Table 8.2
Table 8.3
Table 8.4
Table 8.5
Table 8.6
Section 9 Bus State Controller (BSC)
Table 9.1
Table 9.2
Table 9.3
Section 10 Direct Memory Access Controller (DMAC)
Table 10.1
Table 10.2
Table 10.3
Table 10.4
Table 10.5
Table 10.6
Table 10.7
Table 10.8
Table 10.9
Table 10.10
Section 11 Multi-Function Timer Pulse Unit (MTU)
Table 11.1
Table 11.2
Table 11.3
Table 11.4
Table 11.5
Table 11.6
Table 11.7
Table 11.8
Table 11.9
Table 11.10
Table 11.11
Table 11.12
Rev.4.00 Mar. 27, 2008 Page xl of xliv
REJ09B0108-0400
Interrupt Sources, DTC Vector Addresses, and Corresponding DTEs ................. 124
Normal Mode Register Functions ......................................................................... 127
Repeat Mode Register Functions .......................................................................... 128
Block Transfer Mode Register Functions ............................................................. 129
Execution State of DTC ........................................................................................ 133
State Counts Needed for Execution State ............................................................. 133
Pin Configuration.................................................................................................. 139
Address Map ......................................................................................................... 142
Access to On-chip Peripheral I/O Registers.......................................................... 166
DMAC Pin Configuration..................................................................................... 169
Selecting External Request Modes with RS Bits .................................................. 182
Selecting On-Chip Peripheral Module Request Modes with RS Bits ................... 183
Supported DMA Transfers.................................................................................... 187
Relationship of Request Modes and Bus Modes by DMA Transfer Category ..... 196
Transfer Conditions and Register Set Values for Transfer
Transfer Conditions and Register Set Values for Transfer
Transfer Conditions and Register Set Values for Transfer
DMAC Internal Status .......................................................................................... 209
MTU Functions..................................................................................................... 214
Pin Configuration.................................................................................................. 217
CCLR0 to CCLR2 (Channels 0, 3, and 4) ............................................................ 221
CCLR0 to CCLR2 (Channels 1 and 2) ................................................................. 221
TPSC0 to TPSC2 (Channel 0) .............................................................................. 222
TPSC0 to TPSC2 (Channel 1) .............................................................................. 222
TPSC0 to TPSC2 (Channel 2) .............................................................................. 223
TPSC0 to TPSC2 (Channels 3 and 4) ................................................................... 223
MD0 to MD3 ........................................................................................................ 225
between On-chip SCI and External Memory ........................................................ 206
between External RAM and External Device with DACK................................... 207
between A/D Converter (A/D1) and On-chip Memory ........................................ 208
Transfer Conditions and Register Set Values for Transfer
between External Memory and SCI1 Transmit Side............................................. 210
TIORH_0 (Channel 0) .......................................................................................... 228
TIORL_0 (Channel 0)........................................................................................... 229
TIOR_1 (Channel 1) ............................................................................................. 230