ATSAM3U-EK Atmel, ATSAM3U-EK Datasheet - Page 1015
![KIT EVAL FOR AT91SAM3U CORTEX](/photos/9/20/92037/atsam3u-ek_sml.jpg)
ATSAM3U-EK
Manufacturer Part Number
ATSAM3U-EK
Description
KIT EVAL FOR AT91SAM3U CORTEX
Manufacturer
Atmel
Type
MCUr
Datasheets
1.ATSAM3U-EK.pdf
(2 pages)
2.ATSAM3U-EK.pdf
(61 pages)
3.ATSAM3U-EK.pdf
(1171 pages)
4.ATSAM3U-EK.pdf
(53 pages)
Specifications of ATSAM3U-EK
Contents
Board
Processor To Be Evaluated
SAM3U
Data Bus Width
32 bit
Interface Type
RS-232, USB
Operating Supply Voltage
3 V
Silicon Manufacturer
Atmel
Core Architecture
ARM
Core Sub-architecture
Cortex - M3
Silicon Core Number
SAM3U4E
Silicon Family Name
SAM3U
Kit Contents
Board CD Docs
Rohs Compliant
Yes
For Use With/related Products
AT91SAM3U
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATSAM3U-EK
Manufacturer:
Atmel
Quantity:
10
- ATSAM3U-EK PDF datasheet
- ATSAM3U-EK PDF datasheet #2
- ATSAM3U-EK PDF datasheet #3
- ATSAM3U-EK PDF datasheet #4
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- Download datasheet (25Mb)
Figure 40-2. DMAC Transfer Hierarchy for Non-Memory Peripheral
Figure 40-3. DMAC Transfer Hierarchy for Memory
6430D–ATARM–25-Mar-11
Transfer
AMBA
Transfer
Burst
Buffer
Chunk
FIFO. If the source peripheral is not memory, then a source handshaking interface is assigned to
the channel. If the destination peripheral is not memory, then a destination handshaking inter-
face is assigned to the channel. Source and destination handshaking interfaces can be assigned
dynamically by programming the channel registers.
Master interface: DMAC is a master on the AHB bus reading data from the source and writing it
to the destination over the AHB bus.
Slave interface: The APB interface over which the DMAC is programmed. The slave interface
in practice could be on the same layer as any of the master interfaces or on a separate layer.
Handshaking interface: A set of signal registers that conform to a protocol and handshake
between the DMAC and source or destination peripheral to control the transfer of a single or
chunk transfer between them. This interface is used to request, acknowledge, and control a
DMAC transaction. A channel can receive a request through one of two types of handshaking
interface: hardware or software.
Hardware handshaking interface: Uses hardware signals to control the transfer of a single or
chunk transfer between the DMAC and the source or destination peripheral.
Software handshaking interface: Uses software registers to contr5ol the transfer of a single or
chunk transfer between the DMAC and the source or destination peripheral. No special DMAC
handshaking signals are needed on the I/O of the peripheral. This mode is useful for interfacing
an existing peripheral to the DMAC without modifying it.
Flow controller: The device (either the DMAC or source/destination peripheral) that determines
the length of and terminates a DMAC buffer transfer. If the length of a buffer is known before
enabling the channel, then the DMAC should be programmed as the flow controller.
Transfer hierarchy:
fers, buffer transfers, chunk or single, and AMBA transfers (single or burst) for non-memory
peripherals.
Transfer
AMBA
Transfer
Burst
Chunk
Buffer
HDMA Transfer
Figure 40-3 on page 1015
Figure 40-2 on page 1015
Transfer
AMBA
Burst
Transfer
Chunk
Buffer
Transfer
AMBA
Single
shows the transfer hierarchy for memory.
illustrates the hierarchy between DMAC trans-
Transfer
Transfer
Single
AMBA
Single
DMA Transfer
Level
Buffer Transfer
Level
DMA Transaction
Level
AMBA Transfer
Level
SAM3U Series
1015
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