ATSAM3U-EK Atmel, ATSAM3U-EK Datasheet - Page 887

• Manufacturer Part Number: ATSAM3U-EK
• Description: KIT EVAL FOR AT91SAM3U CORTEX
• Manufacturer: Atmel
• Type: MCUr

Specifications of ATSAM3U-EK

• Contents: Board
• Processor To Be Evaluated: SAM3U
• Data Bus Width: 32 bit
• Interface Type: RS-232, USB
• Operating Supply Voltage: 3 V
• Silicon Manufacturer: Atmel
• Core Architecture: ARM
• Core Sub-architecture: Cortex - M3
• Silicon Core Number: SAM3U4E
• Silicon Family Name: SAM3U
• Kit Contents: Board CD Docs
• Rohs Compliant: Yes
• For Use With/related Products: AT91SAM3U
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

38.6.5
38.6.5.1
6430D–ATARM–25-Mar-11
6430D–ATARM–25-Mar-11
PWM Controller Operations
Initialization
Before enabling the channels, they must have been configured by the software application:
• Unlock User Interface by writing the WPCMD field in the PWM_WPCR Register.
• Configuration of the clock generator (DIVA, PREA, DIVB, PREB in the PWM_CLK register if
• Selection of the clock for each channel (CPRE field in the PWM_CMRx register)
• Configuration of the waveform alignment for each channel (CALG field in the PWM_CMRx
• Selection of the counter event selection (if CALG = 1) for each channel (CES field in the
• Configuration of the output waveform polarity for each channel (CPOL in the PWM_CMRx
• Configuration of the period for each channel (CPRD in the PWM_CPRDx register). Writing in
• Configuration of the duty-cycle for each channel (CDTY in the PWM_CDTYx register).
• Configuration of the dead-time generator for each channel (DTH and DTL in PWM_DTx) if
• Selection of the synchronous channels (SYNCx in the PWM_SCM register)
• Selection of the moment when the WRDY flag and the corresponding PDC transfer request
• Configuration of the update mode (UPDM in the PWM_SCM register)
• Configuration of the update period (UPR in the PWM_SCUP register) if needed.
• Configuration of the comparisons (PWM_CMPVx and PWM_CMPMx).
• Configuration of the event lines (PWM_ELMRx).
• Configuration of the fault inputs polarity (FPOL in PWM_FMR)
• Configuration of the fault protection (FMOD and FFIL in PWM_FMR, PWM_FPV and
• Enable of the Interrupts (writing CHIDx and FCHIDx in PWM_IER1 register, and writing
• Enable of the PWM channels (writing CHIDx in the PWM_ENA register)
required).
register)
PWM_CMRx register)
register)
PWM_CPRDx register is possible while the channel is disabled. After validation of the
channel, the user must use PWM_CPRDUPDx register to update PWM_CPRDx as
explained below.
Writing in PWM_CDTYx register is possible while the channel is disabled. After validation of
the channel, the user must use PWM_CDTYUPDx register to update PWM_CDTYx as
explained below.
enabled (DTE bit in the PWM_CMRx register). Writing in the PWM_DTx register is possible
while the channel is disabled. After validation of the channel, the user must use
PWM_DTUPDx register to update PWM_DTx
are set (PTRM and PTRCS in the PWM_SCM register)
PWM_FPE1)
WRDYE, ENDTXE, TXBUFE, UNRE, CMPMx and CMPUx in PWM_IER2 register)
SAM3U Series
SAM3U Series
887
887