ATSAM3U-EK Atmel, ATSAM3U-EK Datasheet - Page 668

Manufacturer Part Number

KIT EVAL FOR AT91SAM3U CORTEX

Manufacturer

Processor To Be Evaluated

Data Bus Width

Interface Type

Operating Supply Voltage

Silicon Manufacturer

Core Architecture

Core Sub-architecture

Silicon Core Number

Silicon Family Name

Kit Contents

Board CD Docs

Rohs Compliant

For Use With/related Products

Lead Free Status / RoHS Status

Lead free / RoHS Compliant

Manufacturer

Part Number:

Manufacturer:

Figure 34-3. Start Bit Detection

Figure 34-4. Character Reception

Figure 34-5. Receiver Ready

SAM3U Series

Sampling Clock

Receiver Ready

Receiver Overrun

Example: 8-bit, parity enabled 1 stop

When a complete character is received, it is transferred to the UART_RHR and the RXRDY sta-

tus bit in UART_SR (Status Register) is set. The bit RXRDY is automatically cleared when the

receive holding register UART_RHR is read.

If UART_RHR has not been read by the software (or the Peripheral Data Controller) since the

last transfer, the RXRDY bit is still set and a new character is received, the OVRE status bit in

UART_SR is set. OVRE is cleared when the software writes the control register UART_CR with

the bit RSTSTA (Reset Status) at 1.

True Start Detection

Read UART_RHR

6430D–ATARM–25-Mar-11