ATSAM3U-EK Atmel, ATSAM3U-EK Datasheet - Page 28
ATSAM3U-EK
Manufacturer Part Number
ATSAM3U-EK
Description
KIT EVAL FOR AT91SAM3U CORTEX
Manufacturer
Atmel
Type
MCUr
Datasheets
1.ATSAM3U-EK.pdf
(2 pages)
2.ATSAM3U-EK.pdf
(61 pages)
3.ATSAM3U-EK.pdf
(1171 pages)
4.ATSAM3U-EK.pdf
(53 pages)
Specifications of ATSAM3U-EK
Contents
Board
Processor To Be Evaluated
SAM3U
Data Bus Width
32 bit
Interface Type
RS-232, USB
Operating Supply Voltage
3 V
Silicon Manufacturer
Atmel
Core Architecture
ARM
Core Sub-architecture
Cortex - M3
Silicon Core Number
SAM3U4E
Silicon Family Name
SAM3U
Kit Contents
Board CD Docs
Rohs Compliant
Yes
For Use With/related Products
AT91SAM3U
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATSAM3U-EK
Manufacturer:
Atmel
Quantity:
10
- ATSAM3U-EK PDF datasheet
- ATSAM3U-EK PDF datasheet #2
- ATSAM3U-EK PDF datasheet #3
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- Download datasheet (25Mb)
7.6
7.7
28
DMA Controller
Peripheral DMA Controller
SAM3U Series
The DMA controller can handle the transfer between peripherals and memory and so receives
the triggers from the peripherals listed below. The hardware interface numbers are also given in
Table 7-4
Table 7-4.
•
•
•
•
• Acting as one Matrix Master
• Embeds 4 channels:
• Linked List support with Status Write Back operation at End of Transfer
• Word, HalfWord, Byte transfer support.
• Handles high speed transfer of SPI, SSC and HSMCI (peripheral to memory, memory to
• Memory to memory transfer
• Can be triggered by PWM and T/C which enables to generate waveforms though the
peripheral)
External Bus Interface
TIO Output of TImer
Handles data transfer between peripherals and memories
Nineteen channels
–
–
–
–
–
Low bus arbitration overhead
Next Pointer management for reducing interrupt latency requirement
Counter Channel 0
PWM Event Line 0
PWM Event Line 1
– 3 channels with 8 bytes/FIFO for Channel Buffering
– 1 channel with 32 bytes/FIFO for Channel Buffering
– One Master Clock cycle needed for a transfer from memory to peripheral
– Two Master Clock cycles needed for a transfer from peripheral to memory
Instance name
Two for each USART
Two for the UART
Two for each Two Wire Interface
One for the PWM
One for each Analog-to-digital Converter
HSMCI
below.
SSC
SSC
SPI
SPI
DMA Controller
Transmit/Receive
Channel T/R
Transmit
Transmit
Receive
Receive
Trigger
Trigger
Trigger
DMA Channel HW interface
Number
6430D–ATARM–25-Mar-11
0
1
2
3
4
5
6
7
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