ATSAM3U-EK Atmel, ATSAM3U-EK Datasheet - Page 186

Manufacturer Part Number

KIT EVAL FOR AT91SAM3U CORTEX

Manufacturer

Processor To Be Evaluated

Data Bus Width

Interface Type

Operating Supply Voltage

Silicon Manufacturer

Core Architecture

Core Sub-architecture

Silicon Core Number

Silicon Family Name

Kit Contents

Board CD Docs

Rohs Compliant

For Use With/related Products

Lead Free Status / RoHS Status

Lead free / RoHS Compliant

Manufacturer

Part Number:

Manufacturer:

Vector table base offset field. It contains bits[29:7] of the offset of the table base from the bottom of the memory map.

Bit[29] determines whether the vector table is in the code or SRAM memory region:

Bit[29] is sometimes called the TBLBASE bit.

When setting TBLOFF, you must align the offset to the number of exception entries in the vector table. The minimum align-

ment is 32 words, enough for up to 16 interrupts. For more interrupts, adjust the alignment by rounding up to the next power

of two. For example, if you require 21 interrupts, the alignment must be on a 64-word boundary because the required table

size is 37 words, and the next power of two is 64.

Table alignment requirements mean that bits[6:0] of the table offset are always zero.

SAM3U Series

Vector Table Offset Register

The VTOR indicates the offset of the vector table base address from memory address

0x00000000. See the register summary in

The bit assignments are:

Table 13-30 on page 180

for its attributes.

6430D–ATARM–25-Mar-11