ATSAM3U-EK Atmel, ATSAM3U-EK Datasheet - Page 206
ATSAM3U-EK
Manufacturer Part Number
ATSAM3U-EK
Description
KIT EVAL FOR AT91SAM3U CORTEX
Manufacturer
Atmel
Type
MCUr
Datasheets
1.ATSAM3U-EK.pdf
(2 pages)
2.ATSAM3U-EK.pdf
(61 pages)
3.ATSAM3U-EK.pdf
(1171 pages)
4.ATSAM3U-EK.pdf
(53 pages)
Specifications of ATSAM3U-EK
Contents
Board
Processor To Be Evaluated
SAM3U
Data Bus Width
32 bit
Interface Type
RS-232, USB
Operating Supply Voltage
3 V
Silicon Manufacturer
Atmel
Core Architecture
ARM
Core Sub-architecture
Cortex - M3
Silicon Core Number
SAM3U4E
Silicon Family Name
SAM3U
Kit Contents
Board CD Docs
Rohs Compliant
Yes
For Use With/related Products
AT91SAM3U
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATSAM3U-EK
Manufacturer:
Atmel
Quantity:
10
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13.20.15 Auxiliary Fault Status Register
• IMPDEF
Implementation defined. The bits map to the AUXFAULT input signals.
Each AFSR bit maps directly to an AUXFAULT input of the processor, and a single-cycle HIGH signal on the input sets the
corresponding AFSR bit to one. It remains set to 1 until you write 1 to the bit to clear it to zero.
When an AFSR bit is latched as one, an exception does not occur. Use an interrupt if an exception is required.
13.20.16 System control block design hints and tips
206
31
23
15
7
SAM3U Series
30
22
14
6
The AFSR contains additional system fault information. See the register summary in
30 on page 180
This register is read, write to clear. This means that bits in the register read normally, but writing
1 to any bit clears that bit to 0.
The bit assignments are:
Ensure software uses aligned accesses of the correct size to access the system control block
registers:
The processor does not support unaligned accesses to system control block registers.
In a fault handler. to determine the true faulting address:
Software must follow this sequence because another higher priority exception might change the
MMFAR or BFAR value. For example, if a higher priority handler preempts the current fault han-
dler, the other fault might change the MMFAR or BFAR value.
• except for the CFSR and SHPR1-SHPR3, it must use aligned word accesses
• for the CFSR and SHPR1-SHPR3 it can use byte or aligned halfword or word accesses.
• Read and save the MMFAR or BFAR value.
• Read the MMARVALID bit in the MMFSR, or the BFARVALID bit in the BFSR. The MMFAR or
BFAR address is valid only if this bit is 1.
29
21
13
5
for its attributes.
28
20
12
4
IMPDEF
IMPDEF
IMPDEF
IMPDEF
27
19
11
3
26
18
10
2
25
17
9
1
6430D–ATARM–25-Mar-11
Table 13-
24
16
8
0
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