ATSAM3U-EK Atmel, ATSAM3U-EK Datasheet - Page 106
![KIT EVAL FOR AT91SAM3U CORTEX](/photos/9/20/92037/atsam3u-ek_sml.jpg)
ATSAM3U-EK
Manufacturer Part Number
ATSAM3U-EK
Description
KIT EVAL FOR AT91SAM3U CORTEX
Manufacturer
Atmel
Type
MCUr
Datasheets
1.ATSAM3U-EK.pdf
(2 pages)
2.ATSAM3U-EK.pdf
(61 pages)
3.ATSAM3U-EK.pdf
(1171 pages)
4.ATSAM3U-EK.pdf
(53 pages)
Specifications of ATSAM3U-EK
Contents
Board
Processor To Be Evaluated
SAM3U
Data Bus Width
32 bit
Interface Type
RS-232, USB
Operating Supply Voltage
3 V
Silicon Manufacturer
Atmel
Core Architecture
ARM
Core Sub-architecture
Cortex - M3
Silicon Core Number
SAM3U4E
Silicon Family Name
SAM3U
Kit Contents
Board CD Docs
Rohs Compliant
Yes
For Use With/related Products
AT91SAM3U
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATSAM3U-EK
Manufacturer:
Atmel
Quantity:
10
- ATSAM3U-EK PDF datasheet
- ATSAM3U-EK PDF datasheet #2
- ATSAM3U-EK PDF datasheet #3
- ATSAM3U-EK PDF datasheet #4
- Current page: 106 of 1171
- Download datasheet (25Mb)
13.11.2.5
13.11.2.6
13.11.2.7
106
SAM3U Series
Post-indexed addressing
Restrictions
Condition flags
The address obtained from the register Rn is used as the address for the memory access. The
offset value is added to or subtracted from the address, and written back into the register Rn.
The assembly language syntax for this mode is:
The value to load or store can be a byte, halfword, word, or two words. Bytes and halfwords can
either be signed or unsigned. See
Table 13-18
Table 13-18. Offset ranges
For load instructions:
When Rt is PC in a word load instruction:
For store instructions:
These instructions do not change the flags.
Instruction type
Word, halfword, signed
halfword, byte, or signed
byte
Two words
• Rt can be SP or PC for word loads only
• Rt must be different from Rt2 for two-word loads
• Rn must be different from Rt and Rt2 in the pre-indexed or post-indexed forms.
• bit[0] of the loaded value must be 1 for correct execution
• a branch occurs to the address created by changing bit[0] of the loaded value to 0
• if the instruction is conditional, it must be the last instruction in the IT block.
• Rt can be SP for word stores only
• Rt must not be PC
• Rn must not be PC
• Rn must be different from Rt and Rt2 in the pre-indexed or post-indexed forms.
[Rn, #offset]!
[Rn], #offset
shows the ranges of offset for immediate, pre-indexed and post-indexed forms.
Immediate offset
− 255 to 4095
multiple of 4 in the
range − 1020 to
1020
“Address alignment” on page
Pre-indexed
− 255 to 255
multiple of 4 in the
range − 1020 to
1020
99.
Post-indexed
− 255 to 255
multiple of 4 in the
range − 1020 to
1020
6430D–ATARM–25-Mar-11
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