ATSAM3U-EK Atmel, ATSAM3U-EK Datasheet - Page 366

• Manufacturer Part Number: ATSAM3U-EK
• Description: KIT EVAL FOR AT91SAM3U CORTEX
• Manufacturer: Atmel
• Type: MCUr

Specifications of ATSAM3U-EK

• Contents: Board
• Processor To Be Evaluated: SAM3U
• Data Bus Width: 32 bit
• Interface Type: RS-232, USB
• Operating Supply Voltage: 3 V
• Silicon Manufacturer: Atmel
• Core Architecture: ARM
• Core Sub-architecture: Cortex - M3
• Silicon Core Number: SAM3U4E
• Silicon Family Name: SAM3U
• Kit Contents: Board CD Docs
• Rohs Compliant: Yes
• For Use With/related Products: AT91SAM3U
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

25.10.6
25.10.7
25.10.7.1
25.10.7.2
25.11 Scrambling/Unscrambling Function
366
366
SAM3U Series
SAM3U Series
Reset Values of Timing Parameters
Usage Restriction
For Read Operations
For Write Operations
Table 25-7
Table 25-7.
The SMC does not check the validity of the user-programmed parameters. If the sum of SETUP
and PULSE parameters is larger than the corresponding CYCLE parameter, this leads to unpre-
dictable behavior of the SMC.
Null but positive setup and hold of address and NRD and/or NCS can not be guaranteed at the
memory interface because of the propagation delay of theses signals through external logic and
pads. If positive setup and hold values must be verified, then it is strictly recommended to pro-
gram non-null values so as to cover possible skews between address, NCS and NRD signals.
If a null hold value is programmed on NWE, the SMC can guarantee a positive hold of address,
byte select lines, and NCS signal after the rising edge of NWE. This is true for WRITE_MODE =
1 only. See
For read and write operations: a null value for pulse parameters is forbidden and may lead to
unpredictable behavior.
In read and write cycles, the setup and hold time parameters are defined in reference to the
address bus. For external devices that require setup and hold time between NCS and NRD sig-
nals (read), or between NCS and NWE signals (write), these setup and hold times must be
converted into setup and hold times in reference to the address bus.
The external data bus D[15:0] can be scrambled in order to prevent intellectual property data
located in off-chip memories from being easily recovered by analyzing data at the package pin
level of either microcontroller or memory device.
The scrambling and unscrambling are performed on-the-fly without additional wait states.
The scrambling method depends on two user-configurable key registers, SMC_KEY1 and
SMC_KEY2. These key registers are only accessible in write mode.
The key must be securely stored in a reliable non-volatile memory in order to recover data from
the off-chip memory. Any data scrambled with a given key cannot be recovered if the key is lost.
The scrambling/unscrambling function can be enabled or disabled by programming the
SMC_OCMS register.
SMC_SETUP
SMC_PULSE
SMC_CYCLE
WRITE_MODE
READ_MODE
Register
gives the default value of timing parameters at reset.
“Early Read Wait State” on page
Reset Values of Timing Parameters
Reset Value
0x01010101
0x01010101
0x00030003
1
1
Read is controlled with NRD
All setup timings are set to 1
All pulse timings are set to 1
The read and write operation last 3 Master Clock cycles
and provide one hold cycle
Write is controlled with NWE
368.
Description
6430D–ATARM–25-Mar-11
6430D–ATARM–25-Mar-11