ATSAM3U-EK Atmel, ATSAM3U-EK Datasheet - Page 704

• Manufacturer Part Number: ATSAM3U-EK
• Description: KIT EVAL FOR AT91SAM3U CORTEX
• Manufacturer: Atmel
• Type: MCUr

Specifications of ATSAM3U-EK

• Contents: Board
• Processor To Be Evaluated: SAM3U
• Data Bus Width: 32 bit
• Interface Type: RS-232, USB
• Operating Supply Voltage: 3 V
• Silicon Manufacturer: Atmel
• Core Architecture: ARM
• Core Sub-architecture: Cortex - M3
• Silicon Core Number: SAM3U4E
• Silicon Family Name: SAM3U
• Kit Contents: Board CD Docs
• Rohs Compliant: Yes
• For Use With/related Products: AT91SAM3U
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Figure 35-19. FSK Modulator Output
35.7.3.6
35.7.3.7
704
704
Uptstream Frequencies
FSK Modulator
unipolar output
default polarity
[F0, F0+offset]
SAM3U Series
SAM3U Series
NRZ stream
Manchester
encoded
Synchronous Receiver
Receiver Operations
Output
data
Txd
1
In synchronous mode (SYNC = 1), the receiver samples the RXD signal on each rising edge of
the Baud Rate Clock. If a low level is detected, it is considered as a start. All data bits, the parity
bit and the stop bits are sampled and the receiver waits for the next start bit. Synchronous mode
operations provide a high speed transfer capability.
Configuration fields and bits are the same as in asynchronous mode.
Figure 35-20
Figure 35-20. Synchronous Mode Character Reception
When a character reception is completed, it is transferred to the Receive Holding Register
(US_RHR) and the RXRDY bit in the Status Register (US_CSR) rises. If a character is com-
pleted while the RXRDY is set, the OVRE (Overrun Error) bit is set. The last character is
transferred into US_RHR and overwrites the previous one. The OVRE bit is cleared by writing
the Control Register (US_CR) with the RSTSTA (Reset Status) bit to 1.
Example: 8-bit, Parity Enabled 1 Stop
Baud Rate
Sampling
Clock
RXD
illustrates a character reception in synchronous mode.
Start
0
D0
D1
D2
0
D3
D4
D5
D6
D7
1
6430D–ATARM–25-Mar-11
6430D–ATARM–25-Mar-11
Parity Bit
Stop Bit