ATSAM3U-EK Atmel, ATSAM3U-EK Datasheet - Page 1026

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KIT EVAL FOR AT91SAM3U CORTEX

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Processor To Be Evaluated

Data Bus Width

Interface Type

Operating Supply Voltage

Silicon Manufacturer

Core Architecture

Core Sub-architecture

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Kit Contents

Board CD Docs

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Figure 40-7. DMAC Transfer Flow for Source and Destination Linked List Address

SAM3U Series

Multi-buffer DMAC Transfer with Linked List for Source and Contiguous Destination Address (Row 2)

Buffer Complete interrupt

generated here

HDMA Transfer Complete

interrupt generated here

1. Read the Channel Enable register to choose a free (disabled) channel.

2. Set up the linked list in memory. Write the control information in the

LLI.DMAC_CTRLAx and LLI.DMAC_CTRLBx register location of the buffer descriptor

for each LLI in memory for channel x. For example, in the register, you can program the

SADDRx, DADDRx, CTRLA/Bx, DSCRx

Writeback of HDMA_CTRLAx

HDMA State Machine Table?

Hardware reprograms

DMAC buffer transfer

Channel Disabled by

Channel enabled by

6430D–ATARM–25-Mar-11