ATSAM3U-EK Atmel, ATSAM3U-EK Datasheet - Page 234

• Manufacturer Part Number: ATSAM3U-EK
• Description: KIT EVAL FOR AT91SAM3U CORTEX
• Manufacturer: Atmel
• Type: MCUr

Specifications of ATSAM3U-EK

• Contents: Board
• Processor To Be Evaluated: SAM3U
• Data Bus Width: 32 bit
• Interface Type: RS-232, USB
• Operating Supply Voltage: 3 V
• Silicon Manufacturer: Atmel
• Core Architecture: ARM
• Core Sub-architecture: Cortex - M3
• Silicon Core Number: SAM3U4E
• Silicon Family Name: SAM3U
• Kit Contents: Board CD Docs
• Rohs Compliant: Yes
• For Use With/related Products: AT91SAM3U
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

14.4.2
Figure 14-4. Debug Architecture
14.4.3
234
data address sampler
SAM3U Series
Debug Architecture
Serial Wire/JTAG Debug Port (SWJ-DP)
4 watchpoints
interrupt trace
data sampler
CPU statistics
PC sampler
DWT
to low or high level at power up, it must remain in the same state during the duration of the whole
operation.
Figure 14-4
tional units for debug:
The debug architecture information that follows is mainly dedicated to developers of SWJ-DP
Emulators/Probes and debugging tool vendors for Cortex M3-based microcontrollers. For further
details on SWJ-DP see the Cortex M3 technical reference manual.
The Cortex-M3 embeds a SWJ-DP Debug port which is the standard CoreSight
combines Serial Wire Debug Port (SW-DP), from 2 to 3 pins and JTAG debug Port (JTAG-DP),
5 pins.
By default, the JTAG Debug Port is active. If the host debugger wants to switch to the Serial
Wire Debug Port, it must provide a dedicated JTAG sequence on TMS/SWDIO and
TCK/SWCLK which disables JTAG-DP and enables SW-DP.
• SWJ-DP (Serial Wire/JTAG Debug Port)
• FPB (Flash Patch Breakpoint)
• DWT (Data Watchpoint and Trace)
• ITM (Instrumentation Trace Macrocell)
• TPIU (Trace Port Interface Unit)
shows the Debug Architecture used in the SAM3. The Cortex-M3 embeds four func-
software trace
time stamping
6 breakpoints
32 channels
FPB
ITM
TPIU
SWD/JTAG
SWO trace
SWJ-DP
6430D–ATARM–25-Mar-11
™
debug port. It