ATSAM3U-EK Atmel, ATSAM3U-EK Datasheet - Page 71

• Manufacturer Part Number: ATSAM3U-EK
• Description: KIT EVAL FOR AT91SAM3U CORTEX
• Manufacturer: Atmel
• Type: MCUr

Specifications of ATSAM3U-EK

• Contents: Board
• Processor To Be Evaluated: SAM3U
• Data Bus Width: 32 bit
• Interface Type: RS-232, USB
• Operating Supply Voltage: 3 V
• Silicon Manufacturer: Atmel
• Core Architecture: ARM
• Core Sub-architecture: Cortex - M3
• Silicon Core Number: SAM3U4E
• Silicon Family Name: SAM3U
• Kit Contents: Board CD Docs
• Rohs Compliant: Yes
• For Use With/related Products: AT91SAM3U
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

13.4.1.1
13.4.1.2
13.4.1.3
13.4.1.4
13.4.1.5
13.4.2
6430D–ATARM–25-Mar-11
Memory system ordering of memory accesses
Normal
Device
Strongly-ordered
Shareable
Execute Never (XN)
The processor can re-order transactions for efficiency, or perform speculative reads.
The processor preserves transaction order relative to other transactions to Device or Strongly-
ordered memory.
The processor preserves transaction order relative to all other transactions.
The different ordering requirements for Device and Strongly-ordered memory mean that the
memory system can buffer a write to Device memory, but must not buffer a write to Strongly-
ordered memory.
The additional memory attributes include.
For a shareable memory region, the memory system provides data synchronization between
bus masters in a system with multiple bus masters, for example, a processor with a DMA
controller.
Strongly-ordered memory is always shareable.
If multiple bus masters can access a non-shareable memory region, software must ensure data
coherency between the bus masters.
Means the processor prevents instruction accesses. Any attempt to fetch an instruction from an
XN region causes a memory management fault exception.
For most memory accesses caused by explicit memory access instructions, the memory system
does not guarantee that the order in which the accesses complete matches the program order of
the instructions, providing this does not affect the behavior of the instruction sequence. Nor-
mally, if correct program execution depends on two memory accesses completing in program
order, software must insert a memory barrier instruction between the memory access instruc-
tions, see
However, the memory system does guarantee some ordering of accesses to Device and
Strongly-ordered memory. For two memory access instructions A1 and A2, if A1 occurs before
A2 in program order, the ordering of the memory accesses caused by two instructions is:
Where:
- Means that the memory system does not guarantee the ordering of the accesses.
Device access, non-shareable
A1
Device access, shareable
Strongly-ordered access
“Software ordering of memory accesses” on page
Normal access
A2
Normal
access
-
-
-
-
Non-shareable
Device access
<
<
-
-
Shareable
<
<
-
-
73.
SAM3U Series
Strongly-
ordered
access
<
<
<
-
71