ATSAM3U-EK Atmel, ATSAM3U-EK Datasheet - Page 72

KIT EVAL FOR AT91SAM3U CORTEX

ATSAM3U-EK

Manufacturer Part Number
ATSAM3U-EK
Description
KIT EVAL FOR AT91SAM3U CORTEX
Manufacturer
Atmel
Type
MCUr
Datasheets

Specifications of ATSAM3U-EK

Contents
Board
Processor To Be Evaluated
SAM3U
Data Bus Width
32 bit
Interface Type
RS-232, USB
Operating Supply Voltage
3 V
Silicon Manufacturer
Atmel
Core Architecture
ARM
Core Sub-architecture
Cortex - M3
Silicon Core Number
SAM3U4E
Silicon Family Name
SAM3U
Kit Contents
Board CD Docs
Rohs Compliant
Yes
For Use With/related Products
AT91SAM3U
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ATSAM3U-EK
Manufacturer:
Atmel
Quantity:
10
13.4.3
13.4.3.1
72
SAM3U Series
Behavior of memory accesses
Additional memory access constraints for shared memory
< Means that accesses are observed in program order, that is, A1 is always observed before A2.
The behavior of accesses to each region in the memory map is:
Table 13-4.
1.
The Code, SRAM, and external RAM regions can hold programs. However, ARM recommends
that programs always use the Code region. This is because the processor has separate buses
that enable instruction fetches and data accesses to occur simultaneously.
The MPU can override the default memory access behavior described in this section. For more
information, see
When a system includes shared memory, some memory regions have additional access con-
straints, and some regions are subdivided, as
Table 13-5.
Address
range
0x00000000-
0x1FFFFFFF
0x20000000-
0x3FFFFFFF
0x40000000-
0x5FFFFFFF
0x60000000-
0x9FFFFFFF
0xA0000000-
0xDFFFFFFF
0xE0000000-
0xE00FFFFF
0xE0100000-
0xFFFFFFFF
Address range
0x00000000-
0x1FFFFFFF
0x20000000-
0x3FFFFFFF
0x40000000-
0x5FFFFFFF
See
“Memory regions, types and attributes” on page 70
Memory access behavior
Memory region share ability policies
Memory
region
Code
SRAM
Peripheral
External
RAM
External
device
Private
Peripheral
Bus
Reserved
“Memory protection unit” on page
Memory region
Code
SRAM
Peripheral
Memory
type
Normal
Normal
Device
Normal
Device
Strongly-
ordered
Device
(2)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
XN
-
-
XN
-
XN
XN
XN
Memory type
Normal
Normal
Device
Table 13-5
Description
Executable region for program code. You can also put
data here.
Executable region for data. You can also put code
here.
This region includes bit band and bit band alias areas,
see
This region includes bit band and bit band alias areas,
see
Executable region for data.
External Device memory
This region includes the NVIC, System timer, and
system control block.
Reserved
Table 13-6 on page
Table 13-6 on page
212.
(1)
(1)
(1)
shows:
for more information.
Shareability
-
-
-
74.
74.
6430D–ATARM–25-Mar-11

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