ATSAM3U-EK Atmel, ATSAM3U-EK Datasheet - Page 360

• Manufacturer Part Number: ATSAM3U-EK
• Description: KIT EVAL FOR AT91SAM3U CORTEX
• Manufacturer: Atmel
• Type: MCUr

Specifications of ATSAM3U-EK

• Contents: Board
• Processor To Be Evaluated: SAM3U
• Data Bus Width: 32 bit
• Interface Type: RS-232, USB
• Operating Supply Voltage: 3 V
• Silicon Manufacturer: Atmel
• Core Architecture: ARM
• Core Sub-architecture: Cortex - M3
• Silicon Core Number: SAM3U4E
• Silicon Family Name: SAM3U
• Kit Contents: Board CD Docs
• Rohs Compliant: Yes
• For Use With/related Products: AT91SAM3U
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

25.10 Standard Read and Write Protocols
25.10.1
Figure 25-7. Standard Read Cycle
25.10.1.1
360
360
SAM3U Series
SAM3U Series
Read Waveforms
NRD Waveform
NBS0,NBS1,
A0, A1
D[15:0]
A[23:2]
MCK
NRD
NCS
In the following sections, the byte access type is not considered. Byte select lines (NBS0 to
NBS1) always have the same timing as the A address bus. NWE represents either the NWE sig-
nal in byte select access type or one of the byte write lines (NWR0 to NWR1) in byte write
access type. NWR0 to NWR3 have the same timings and protocol as NWE. In the same way,
NCS represents one of the NCS[0..3] chip select lines.
The read cycle is shown on
The read cycle starts with the address setting on the memory address bus, i.e.:
The NRD signal is characterized by a setup timing, a pulse width and a hold timing.
1. NRD_SETUP: the NRD setup time is defined as the setup of address before the NRD
2. NRD_PULSE: the NRD pulse length is the time between NRD falling edge and NRD
3. NRD_HOLD: the NRD hold time is defined as the hold time of address after the NRD
NCS_RD_SETUP
falling edge.
rising edge.
rising edge.
{A[23:2], A1, A0} for 8-bit devices
{A[23:2], A1} for 16-bit devices
NRD_SETUP
Figure
NCS_RD_PULSE
NRD_CYCLE
NRD_PULSE
25-7.
NRD_HOLD
NCS_RD_HOLD
6430D–ATARM–25-Mar-11
6430D–ATARM–25-Mar-11