ATSAM3U-EK Atmel, ATSAM3U-EK Datasheet - Page 938

• Manufacturer Part Number: ATSAM3U-EK
• Description: KIT EVAL FOR AT91SAM3U CORTEX
• Manufacturer: Atmel
• Type: MCUr

Specifications of ATSAM3U-EK

• Contents: Board
• Processor To Be Evaluated: SAM3U
• Data Bus Width: 32 bit
• Interface Type: RS-232, USB
• Operating Supply Voltage: 3 V
• Silicon Manufacturer: Atmel
• Core Architecture: ARM
• Core Sub-architecture: Cortex - M3
• Silicon Core Number: SAM3U4E
• Silicon Family Name: SAM3U
• Kit Contents: Board CD Docs
• Rohs Compliant: Yes
• For Use With/related Products: AT91SAM3U
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

38.7.39
Name:
Address:
Access:
This register can only be written if the bits WPSWS3 and WPHWS3 are cleared in
page
This register acts as a double buffer for the CPRD value. This prevents an unexpected waveform when modifying the
waveform period.
Only the first 16 bits (channel counter size) are significant.
• CPRDUPD: Channel Period Update
If the waveform is left-aligned, then the output waveform period depends on the channel counter source clock and can be
calculated:
If the waveform is center-aligned, then the output waveform period depends on the channel counter source clock and can
be calculated:
938
938
928.
– By using the PWM master clock (MCK) divided by an X given prescaler value (with X being 1, 2, 4, 8, 16, 32,
– By using the PWM master clock (MCK) divided by one of both DIVA or DIVB divider, the formula becomes,
– By using the PWM master clock (MCK) divided by an X given prescaler value (with X being 1, 2, 4, 8, 16, 32,
– By using the PWM master clock (MCK) divided by one of both DIVA or DIVB divider, the formula becomes,
31
23
15
–
7
64, 128, 256, 512, or 1024). The resulting period formula will be:
respectively:
64, 128, 256, 512, or 1024). The resulting period formula will be:
(
------------------------------------------------------- -
respectively:
(
------------------------------------------------------------------ -
(
---------------------------------------------
2
2
X
(
-------------------------------------------------------- -
CRPDUPD
SAM3U Series
SAM3U Series
×
×
×
PWM Channel Period Update Register
X
CPRDUPD
CPRDUPD
MCK
×
PWM_CPRDUPDx [x=0..3]
0x4008C210 [0], 0x4008C230 [1], 0x4008C250 [2], 0x4008C270 [3]
Write-only
MCK
CPRDUPD
MCK
MCK
×
30
22
14
DIVA
–
6
)
×
DIVA
)
)
or
)
or
(
-------------------------------------------------------- -
CRPDUPD
(
------------------------------------------------------------------ -
2
×
29
21
13
–
5
CPRDUPD
MCK
MCK
×
DIVB
×
)
DIVB
28
20
12
–
4
CPRDUPD
CPRDUPD
CPRDUPD
)
27
19
11
–
3
“PWM Write Protect Status Register” on
26
18
10
–
2
25
17
–
9
1
6430D–ATARM–25-Mar-11
6430D–ATARM–25-Mar-11
24
16
–
8
0