ATSAM3U-EK Atmel, ATSAM3U-EK Datasheet - Page 1057

• Manufacturer Part Number: ATSAM3U-EK
• Description: KIT EVAL FOR AT91SAM3U CORTEX
• Manufacturer: Atmel
• Type: MCUr

Specifications of ATSAM3U-EK

• Contents: Board
• Processor To Be Evaluated: SAM3U
• Data Bus Width: 32 bit
• Interface Type: RS-232, USB
• Operating Supply Voltage: 3 V
• Silicon Manufacturer: Atmel
• Core Architecture: ARM
• Core Sub-architecture: Cortex - M3
• Silicon Core Number: SAM3U4E
• Silicon Family Name: SAM3U
• Kit Contents: Board CD Docs
• Rohs Compliant: Yes
• For Use With/related Products: AT91SAM3U
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

41.4.7
41.5
41.5.1
41.5.2
41.5.3
41.5.4
6430D–ATARM–25-Mar-11
Functional Description
Conversion Performances
Analog-to-digital Conversion
Conversion Reference
Conversion Resolution
Differential Inputs
For performance and electrical characteristics of the ADC12B, see the DC Characteristics sec-
tion of the product datasheet.
The ADC12B uses the ADC12B Clock to perform conversions. Converting a single analog value
to 12-bit digital data requires Sample and Hold Clock cycles as defined in the SHTIM field of the
“ADC12B Mode Register” on page 1066
quency is selected in the PRESCAL field of the Mode Register (ADC12B_MR).
The ADC12B clock range is between MCK/2, if PRESCAL is 0, and MCK/128, if PRESCAL is
set to 63 (0x3F). PRESCAL must be programmed in order to provide an ADC12B clock fre-
quency according to the parameters given in the Electrical Characteristics section of the product
datasheet.
The conversion is performed on a full range between 0V and the reference voltage pin
AD12BVREF Analog inputs between these voltages convert to values based on a linear
conversion.
The ADC12B supports 10-bit or 12-bit resolution. The 10-bit selection is performed by setting the
LOWRES bit in the ADC12B Mode Register (ADC12B_MR). By default, after a reset, the resolu-
tion is the highest and the DATA field in the data registers is fully used. By setting the LOWRES
bit, the ADC12B switches in the lowest resolution and the conversion results can be read in the
eight lowest significant bits of the data registers. The two highest bits of the DATA field in the
corresponding ADC12B_CDR register and of the LDATA field in the ADC12B_LCDR register
read 0.
Moreover, when a PDC channel is connected to the ADC12B, 12-bit or 10-bit resolution sets the
transfer request size to 16 bits.
The ADC12B can be used either as a single ended ADC12B (DIFF bit equal to 0) or as a fully
differential ADC12B (DIFF bit equal to 1) as shown in
ADC12B is in single ended mode.
The same inputs are used in single ended or differential mode.
In single ended mode, inputs are managed by an 8:1 channels analog multiplexer. In the fully
differential mode, inputs are managed by a 4:1 channels analog multiplexer. See
Table
41-5.
and 10 ADC12B Clock cycles. The ADC12B Clock fre-
Figure
41-2. By default, after a reset, the
SAM3U Series
Table 41-4
1057
and