ATSAM3U-EK Atmel, ATSAM3U-EK Datasheet - Page 884
ATSAM3U-EK
Manufacturer Part Number
ATSAM3U-EK
Description
KIT EVAL FOR AT91SAM3U CORTEX
Manufacturer
Atmel
Type
MCUr
Datasheets
1.ATSAM3U-EK.pdf
(2 pages)
2.ATSAM3U-EK.pdf
(61 pages)
3.ATSAM3U-EK.pdf
(1171 pages)
4.ATSAM3U-EK.pdf
(53 pages)
Specifications of ATSAM3U-EK
Contents
Board
Processor To Be Evaluated
SAM3U
Data Bus Width
32 bit
Interface Type
RS-232, USB
Operating Supply Voltage
3 V
Silicon Manufacturer
Atmel
Core Architecture
ARM
Core Sub-architecture
Cortex - M3
Silicon Core Number
SAM3U4E
Silicon Family Name
SAM3U
Kit Contents
Board CD Docs
Rohs Compliant
Yes
For Use With/related Products
AT91SAM3U
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATSAM3U-EK
Manufacturer:
Atmel
Quantity:
10
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38.6.3
884
884
SAM3U Series
SAM3U Series
PWM Comparison Units
The PWM provides 8 independent comparison units able to compare a programmed value with
the current value of the channel 0 counter (which is the channel counter of all synchronous
channels,
erate pulses on the event lines (used to synchronize ADC, see
Lines”), to generate software interrupts and to trigger PDC transfer requests for the synchronous
channels (see
update” on page
Figure 38-13. Comparison Unit Block Diagram
The comparison x matches when it is enabled by the bit CEN in the
Register”
the comparison value defined by the field CV in
(PWM_CMPVx for the comparison x). If the counter of the channel 0 is center aligned (CALG =
1 in
made when the counter is counting up or counting down (in left alignment mode CALG=0, this
bit is useless).
If a fault is active on the channel 0, the comparison is disabled and cannot match (see
38.6.2.5 ”Fault
The user can define the periodicity of the comparison x by the fields CTR and CPR (in
PWM_CMPVx). The comparison is performed periodically once every CPR+1 periods of the
counter of the channel 0, when the value of the comparison period counter CPRCNT (in
PWM_CMPMx) reaches the value defined by CTR. CPR is the maximum value of the compari-
son period counter CPRCNT. If CPR=CTR=0, the comparison is performed at each period of the
counter of the channel 0.
The comparison x configuration can be modified while the channel 0 is enabled by using the
“PWM Comparison x Mode Update Register”
x). In the same way, the comparison x value can be modified while the channel 0 is enabled by
using the
comparison x).
“PWM Channel Mode
(PWM_CMPMx for the comparison x) and when the counter of the channel 0 reaches
Section 38.6.2.6 ”Synchronous
“PWM Comparison x Value Update Register”
Protection”).
CEN [PWM_CMPM]x
fault on channel 0
CV [PWM_CMPVx]
CNT [PWM_CCNT0]
CNT [PWM_CCNT0] is decrementing
CVM [PWM_CMPVx]
CALG [PWM_CMR0]
CPRCNT [PWM_CMPMx]
CTR [PWM_CMPMx]
“Method 3: Automatic write of duty-cycle values and automatic trigger of the
881).
Register”), the bit CVM (in PWM_CMPVx) defines if the comparison is
Channels”). These comparisons are intended to gen-
=
=
=
(PWM_CMPMUPDx registers for the comparison
1
0
1
“PWM Comparison x Value Register”
(PWM_CMPVUPDx registers for the
Section 38.6.4 ”PWM Event
“PWM Comparison x Mode
Comparison x
6430D–ATARM–25-Mar-11
6430D–ATARM–25-Mar-11
Section
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