ATSAM3U-EK Atmel, ATSAM3U-EK Datasheet - Page 625

• Manufacturer Part Number: ATSAM3U-EK
• Description: KIT EVAL FOR AT91SAM3U CORTEX
• Manufacturer: Atmel
• Type: MCUr

Specifications of ATSAM3U-EK

• Contents: Board
• Processor To Be Evaluated: SAM3U
• Data Bus Width: 32 bit
• Interface Type: RS-232, USB
• Operating Supply Voltage: 3 V
• Silicon Manufacturer: Atmel
• Core Architecture: ARM
• Core Sub-architecture: Cortex - M3
• Silicon Core Number: SAM3U4E
• Silicon Family Name: SAM3U
• Kit Contents: Board CD Docs
• Rohs Compliant: Yes
• For Use With/related Products: AT91SAM3U
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

33.7
33.7.1
33.7.2
Figure 33-5. Master Mode Typical Application Block Diagram
33.7.3
33.7.4
6430D–ATARM–25-Mar-11
Master Mode
Definition
Application Block Diagram
Programming Master Mode
Master Transmitter Mode
Rp: Pull up value as given by the I²C Standard
Host with
Interface
TWI
The Master is the device that starts a transfer, generates a clock and stops it.
The following registers have to be programmed before entering Master mode:
After the master initiates a Start condition when writing into the Transmit Holding Register,
TWI_THR, it sends a 7-bit slave address, configured in the Master Mode register (DADR in
TWI_MMR), to notify the slave device. The bit following the slave address indicates the transfer
direction, 0 in this case (MREAD = 0 in TWI_MMR).
The TWI transfers require the slave to acknowledge each received byte. During the acknowl-
edge clock pulse (9th pulse), the master releases the data line (HIGH), enabling the slave to pull
it down in order to generate the acknowledge. The master polls the data line during this clock
pulse and sets the Not Acknowledge bit (NACK) in the status register if the slave does not
acknowledge the byte. As with the other status bits, an interrupt can be generated if enabled in
the interrupt enable register (TWI_IER). If the slave acknowledges the byte, the data written in
the TWI_THR, is then shifted in the internal shifter and transferred. When an acknowledge is
detected, the TXRDY bit is set until a new write in the TWI_THR.
While no new data is written in the TWI_THR, the Serial Clock Line is tied low. When new data is
written in the TWI_THR, the SCL is released and the data is sent. To generate a STOP event,
the STOP command must be performed by writing in the STOP field of TWI_CR.
TWD
TWCK
1. DADR (+ IADRSZ + IADR if a 10 bit device is addressed): The device address is used
2. CKDIV + CHDIV + CLDIV: Clock Waveform.
3. SVDIS: Disable the slave mode.
4. MSEN: Enable the master mode.
Serial EEPROM
to access slave devices in read or write mode.
Atmel TWI
Slave 1
I²C RTC
Slave 2
Controller
I²C LCD
Slave 3
I²C Temp.
Slave 4
Sensor
Rp
SAM3U Series
Rp
VDD
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