MPC8544DS Freescale Semiconductor, MPC8544DS Datasheet - Page 1051

• Manufacturer Part Number: MPC8544DS
• Description: BOARD DEVELOPMENT SYSTEM 8544
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8544DS

• Contents: Board
• Processor To Be Evaluated: MPC8544E
• Data Bus Width: 32 bit
• Interface Type: Ethernet, I2C
• Operating Supply Voltage: - 0.3 V to + 1.1 V
• Leaded Process Compatible: Yes
• Peak Reflow Compatible (260 C): Yes
• Rohs Compliant: Yes
• For Use With/related Products: MPC8544
• For Use With: PPC8544EVTANG - EVAL MPC8544 783FCPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Detected Parity Error on upper
Detected Parity Error on upper
17.5
This section describes some tips for use of the PCI controller.
17.5.1
The PCI controller can power-on in three modes: host mode, agent mode and agent configuration lock
mode. Certain bits in the configuration registers are set differently according to the POR (power-on reset)
mode. Also, certain configuration bits have different implications when compared with past Freescale
parts and PCI implementations. Note that after reset, the device cannot be switched from one mode to
another.
The affected configuration bits are defined in
Freescale Semiconductor
Received PERR (Data phase)
Received SERR at any phase Received SERR
Received SERR at any phase
Detected Parity Error for Data
Register (offset) Bit
address bus for Address
Detected Parity Error for
address bus for Address
phase (SAC or DAC)
phase (SAC or DAC)
Command
Register
PCI Error Type
Address phase
(0x04)
Internal error
PCI
Initialization/Application Information
phase
Power-On Reset Configuration Modes
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
2
1 Memory
master
Name
space
Bus
Table 17-53. Affected Configuration Register Bits for POR
Addr Parity Error Detected Parity Error,
Target PERR
Error Detect
Register bit
Target Abort
Rcvd SERR
Table 17-52. PCI Mode Error Actions (continued)
Trgt PERR
Controls whether the device can master a transaction on the PCI bus. If cleared, the device
can not master a transaction. This bit is independent of host or agent mode.
Controls the acknowledgement of inbound memory transactions. If cleared, all inbound
memory accesses (including accesses to PCSRBAR space) end in a master abort. This bit
is independent of host or agent mode.
—
—
Signaled System Error
Signaled Target Abort
Detected Parity Error Cache line purged
PCI Inbound Write
Register bit
PCI Status
Table
—
—
—
—
—
17-53.
Register Description
Cache line purged
Comment
PCI Bus Interface
17-67