MPC8544DS Freescale Semiconductor, MPC8544DS Datasheet - Page 37

• Manufacturer Part Number: MPC8544DS
• Description: BOARD DEVELOPMENT SYSTEM 8544
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8544DS

• Contents: Board
• Processor To Be Evaluated: MPC8544E
• Data Bus Width: 32 bit
• Interface Type: Ethernet, I2C
• Operating Supply Voltage: - 0.3 V to + 1.1 V
• Leaded Process Compatible: Yes
• Peak Reflow Compatible (260 C): Yes
• Rohs Compliant: Yes
• For Use With/related Products: MPC8544
• For Use With: PPC8544EVTANG - EVAL MPC8544 783FCPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Paragraph
Number
18.1.3
18.1.3.1
18.1.3.2
18.2
18.3
18.3.1
18.3.2
18.3.2.1
18.3.2.2
18.3.2.3
18.3.2.4
18.3.2.5
18.3.3
18.3.3.1
18.3.3.2
18.3.3.3
18.3.3.4
18.3.4
18.3.4.1
18.3.4.2
18.3.5
18.3.5.1
18.3.5.1.1
18.3.5.1.2
18.3.5.1.3
18.3.5.1.4
18.3.5.2
18.3.5.2.1
18.3.5.2.2
18.3.5.2.3
18.3.5.2.4
18.3.5.2.5
18.3.5.2.6
18.3.6
Freescale Semiconductor
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
External Signal Descriptions ......................................................................................... 18-4
Memory Map/Register Definitions ................................................................................ 18-5
Modes of Operation ................................................................................................... 18-4
PCI Express Memory Mapped Registers................................................................... 18-5
PCI Express Configuration Access Registers............................................................ 18-9
PCI Express Power Management Event and Message Registers ............................ 18-13
PCI Express IP Block Revision Registers ............................................................... 18-18
PCI Express ATMU Registers ................................................................................. 18-19
PCI Express Error Management Registers .............................................................. 18-29
Root Complex/Endpoint Modes ............................................................................ 18-4
Link Width ............................................................................................................. 18-4
PCI Express Configuration Address Register (PEX_CONFIG_ADDR) .............. 18-9
PCI Express Configuration Data Register (PEX_CONFIG_DATA)................... 18-10
PCI Express Outbound Completion Timeout Register
PCI Express Configuration Retry Timeout Register
PCI Express Configuration Register (PEX_CONFIG)........................................ 18-12
PCI Express PME and Message Detect Register (PEX_PME_MES_DR) ......... 18-13
PCI Express PME and Message Disable Register
PCI Express PME and Message Interrupt Enable Register
PCI Express Power Management Command Register (PEX_PMCR) ................ 18-17
IP Block Revision Register 1 (PEX_IP_BLK_REV1)........................................ 18-18
IP Block Revision Register 2 (PEX_IP_BLK_REV2)........................................ 18-19
PCI Express Outbound ATMU Registers ............................................................ 18-19
PCI Express Inbound ATMU Registers ............................................................... 18-24
(PEX_OTB_CPL_TOR).................................................................................. 18-11
(PEX_CONF_RTY_TOR)............................................................................... 18-11
(PEX_PME_MES_DISR) ............................................................................... 18-14
(PEX_PME_MES_IER) .................................................................................. 18-16
PCI Express Outbound Translation Address Registers (PEXOTARn) ........... 18-20
PCI Express Outbound Translation Extended Address Registers
PCI Express Outbound Window Base Address Registers
PCI Express Outbound Window Attributes Registers (PEXOWARn)............ 18-22
EP Inbound ATMU Implementation................................................................ 18-24
RC Inbound ATMU Implementation ............................................................... 18-25
PCI Express Inbound Translation Address Registers (PEXITARn)................ 18-25
PCI Express Inbound Window Base Address Registers (PEXIWBARn) ....... 18-26
PCI Express Inbound Window Base Extended Address Registers
PCI Express Inbound Window Attributes Registers (PEXIWARn) ................ 18-27
(PEXOTEARn)............................................................................................ 18-21
(PEXOWBARn) .......................................................................................... 18-21
(PEXIWBEARn) ......................................................................................... 18-27
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