MPC8544DS Freescale Semiconductor, MPC8544DS Datasheet - Page 71
MPC8544DS
Manufacturer Part Number
MPC8544DS
Description
BOARD DEVELOPMENT SYSTEM 8544
Manufacturer
Freescale Semiconductor
Series
PowerQUICC III™r
Type
MPUr
Datasheets
1.MPC8544VTALF.pdf
(117 pages)
2.MPC8544VTALF.pdf
(2 pages)
3.MPC8544VTALF.pdf
(1340 pages)
4.MPC8544DS.pdf
(2 pages)
Specifications of MPC8544DS
Contents
Board
Processor To Be Evaluated
MPC8544E
Data Bus Width
32 bit
Interface Type
Ethernet, I2C
Operating Supply Voltage
- 0.3 V to + 1.1 V
Leaded Process Compatible
Yes
Peak Reflow Compatible (260 C)
Yes
Rohs Compliant
Yes
For Use With/related Products
MPC8544
For Use With
PPC8544EVTANG - EVAL MPC8544 783FCPBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
- MPC8544VTALF PDF datasheet
- MPC8544VTALF PDF datasheet #2
- MPC8544VTALF PDF datasheet #3
- MPC8544DS PDF datasheet #4
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- Download datasheet (12Mb)
Table
Number
9-20
9-21
9-22
9-23
9-24
9-25
9-26
9-27
9-28
9-29
9-30
9-31
9-32
9-33
9-34
9-35
9-36
9-37
9-38
9-39
9-40
9-41
9-42
9-43
9-44
9-45
9-46
9-47
9-48
9-49
9-50
9-51
9-52
9-53
9-54
10-1
10-2
10-3
10-4
Freescale Semiconductor
DDR_SDRAM_CLK_CNTL Field Descriptions ................................................................. 9-30
DDR_INIT_ADDR Field Descriptions ................................................................................ 9-31
DDR_INIT_EXT_ADDR Field Descriptions....................................................................... 9-31
DDR_IP_REV1 Field Descriptions ...................................................................................... 9-32
DDR_IP_REV2 Field Descriptions ...................................................................................... 9-32
DATA_ERR_INJECT_HI Field Descriptions....................................................................... 9-33
DATA_ERR_INJECT_LO Field Descriptions ..................................................................... 9-33
ERR_INJECT Field Descriptions ......................................................................................... 9-34
CAPTURE_DATA_HI Field Descriptions............................................................................ 9-34
CAPTURE_DATA_LO Field Descriptions........................................................................... 9-35
CAPTURE_ECC Field Descriptions .................................................................................... 9-35
ERR_DETECT Field Descriptions ....................................................................................... 9-36
ERR_DISABLE Field Descriptions...................................................................................... 9-37
ERR_INT_EN Field Descriptions ........................................................................................ 9-38
CAPTURE_ATTRIBUTES Field Descriptions .................................................................... 9-38
CAPTURE_ADDRESS Field Descriptions .......................................................................... 9-40
CAPTURE_EXT_ADDRESS Field Descriptions ................................................................ 9-40
ERR_SBE Field Descriptions ............................................................................................... 9-41
Byte Lane to Data Relationship ............................................................................................ 9-45
Supported DDR2 SDRAM Device Configurations .............................................................. 9-46
DDR1 Address Multiplexing for 64-Bit Data Bus with Interleaving Disabled .................... 9-47
DDR1 Address Multiplexing for 32-Bit Data Bus with Interleaving Disabled .................... 9-48
DDR2 Address Multiplexing for 64-Bit Data Bus with Interleaving Disabled .................... 9-49
DDR2 Address Multiplexing for 32-Bit Data Bus with Interleaving Disabled .................... 9-50
Example of Address Multiplexing for 64-Bit Data Bus Interleaving Between
Example of Address Multiplexing for 64-Bit Data Bus Interleaving
DDR SDRAM Command Table............................................................................................ 9-53
DDR SDRAM Interface Timing Intervals ............................................................................ 9-54
DDR SDRAM Power-Saving Modes Refresh Configuration............................................... 9-62
Memory Controller–Data Beat Ordering .............................................................................. 9-64
DDR SDRAM ECC Syndrome Encoding ............................................................................ 9-65
DDR SDRAM ECC Syndrome Encoding (Check Bits) ....................................................... 9-67
Memory Controller Errors .................................................................................................... 9-68
Memory Interface Configuration Register Initialization Parameters.................................... 9-68
Programming Differences Between Memory Types............................................................. 9-69
Processor Interrupts Generated Outside the Core—Types and Sources ............................... 10-3
e500 Core-Generated Interrupts that Cause a Wake-Up ....................................................... 10-4
Internal Interrupt Sources...................................................................................................... 10-6
PIC Interface Signals ............................................................................................................ 10-7
Two Banks........................................................................................................................ 9-51
Between Four Banks ........................................................................................................ 9-52
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Tables
Title
Number
Page
lxxi
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