MPC8544DS Freescale Semiconductor, MPC8544DS Datasheet - Page 268
MPC8544DS
Manufacturer Part Number
MPC8544DS
Description
BOARD DEVELOPMENT SYSTEM 8544
Manufacturer
Freescale Semiconductor
Series
PowerQUICC III™r
Type
MPUr
Datasheets
1.MPC8544VTALF.pdf
(117 pages)
2.MPC8544VTALF.pdf
(2 pages)
3.MPC8544VTALF.pdf
(1340 pages)
4.MPC8544DS.pdf
(2 pages)
Specifications of MPC8544DS
Contents
Board
Processor To Be Evaluated
MPC8544E
Data Bus Width
32 bit
Interface Type
Ethernet, I2C
Operating Supply Voltage
- 0.3 V to + 1.1 V
Leaded Process Compatible
Yes
Peak Reflow Compatible (260 C)
Yes
Rohs Compliant
Yes
For Use With/related Products
MPC8544
For Use With
PPC8544EVTANG - EVAL MPC8544 783FCPBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
- MPC8544VTALF PDF datasheet
- MPC8544VTALF PDF datasheet #2
- MPC8544VTALF PDF datasheet #3
- MPC8544DS PDF datasheet #4
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- Download datasheet (12Mb)
Core Register Summary
6.15.2
6-50
Reset
56–63
Bits
Bits
55
32
33
34
35
36
W
R
PMLCa0 (PMR144)
PMLCa1 (PMR145)
PMLCa2 (PMR146)
PMLCa3 (PMR147)
FC FCS FCU FCM1 FCM0 CE
32
Figure 6-59. Local Control A Registers (PMLCa0–PMLCa3), User Local Control A Registers
Name
FCM1 Freeze counter while mark = 1
FCM0 Freeze counter while mark = 0
FCU
Name
FCS
TBEE
FC
33
—
Local Control A Registers
(PMLCa0–PMLCa3, UPMLCa0–UPMLCa3)
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
34
Freeze counter
0 The PMC is incremented (if permitted by other PM control bits).
1 The PMC is not incremented.
Freeze counter in supervisor state
0 The PMC is incremented (if permitted by other PM control bits).
1 The PMC is not incremented if MSR[PR] = 0.
Freeze counter in user state
0 The PMC is incremented (if permitted by other PM control bits).
1 The PMC is not incremented if MSR[PR] = 1.
0 The PMC is incremented (if permitted by other PM control bits).
1 The PMC is not incremented if MSR[PMM] = 1.
0 The PMC is incremented (if permitted by other PM control bits).
1 The PMC is not incremented if MSR[PMM] = 0.
0 Exceptions from time base transition events are disabled.
1 Exceptions from time base transition events are enabled. A timebase transition is signaled to the
Time base transition event exception enable.
Reserved, should be cleared.
performance monitor if the TB bit specified in PMGC0[TBSEL] changes from 0 to 1. Timebase transition
events can be used to freeze the counters (PMGC0[FCECE]) or signal an exception (PMGC0[PMIE]).
Changing PMGC0[TBSEL] while PMGC0[TBEE] is enabled may cause a false 0 to 1 transition that
signals the specified action (freeze, exception) to occur immediately. Although the interrupt signal
condition may occur with MSR[EE] = 0, the interrupt cannot be taken until MSR[EE] = 1.
35
36
Table 6-43. PMGC0 Field Descriptions (continued)
Table 6-44. PMLCa0–PMLCa3 Field Descriptions
UPMLCa0 (PMR128)
UPMLCa1 (PMR129)
UPMLCa2 (PMR130)
UPMLCa3 (PMR131)
37 38
—
40 41
(UPMLCa0–UPMLCa3)
EVENT
All zeros
Description
Description
47 48
Access: PMLCa0–PMLCa3: Supervisor read/write
UPMLCa0–UPMLCa3: Supervisor/user read only
—
Freescale Semiconductor
63
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