MPC8544DS Freescale Semiconductor, MPC8544DS Datasheet - Page 195

• Manufacturer Part Number: MPC8544DS
• Description: BOARD DEVELOPMENT SYSTEM 8544
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8544DS

• Contents: Board
• Processor To Be Evaluated: MPC8544E
• Data Bus Width: 32 bit
• Interface Type: Ethernet, I2C
• Operating Supply Voltage: - 0.3 V to + 1.1 V
• Leaded Process Compatible: Yes
• Peak Reflow Compatible (260 C): Yes
• Rohs Compliant: Yes
• For Use With/related Products: MPC8544
• For Use With: PPC8544EVTANG - EVAL MPC8544 783FCPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Freescale Semiconductor
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— Two general-purpose read data buses and one write data bus
Extended exception handling
— Supports embedded category interrupt model
Memory management unit (MMU)
— 32-bit effective address translated to 32-bit real address (using a 41-bit interim virtual address)
— TLB entries for variable- (4-Kbyte–256-Mbyte pages for the e500v1 and 4-Kbyte–4-Gbyte
— Data L1 MMU
— Instruction L1 MMU
— Unified L2 MMU
— Software reload for TLBs
— Virtual memory support for as much as 4 Gbytes (2
— Real memory support for as much as 4 Gbytes (2
— Support for big-endian and true little-endian memory on a per-page basis
Power management
— Low-power design
– Less than 10-cycle interrupt latency
– Interrupt vector prefix register (IVPR)
– Interrupt vector offset registers (IVORs) 0–15 and 32–35
– Exception syndrome register (ESR)
– Preempting critical interrupt, including critical interrupt status registers (CSRR0 and
– A separate set of resources for machine-check interrupts
– SPE unavailable exception
– Floating-point data exception
– Floating-point round exception
– Performance monitor
for the e500v1core and 36-bit real addressing for the e500v2 core
pages for the e500v2) and fixed-size (4-Kbyte) pages
– 4-entry, fully-associative TLB array for variable-sized pages
– 64-entry, 4-way set-associative TLB for 4-Kbyte pages
– 4-entry, fully-associative TLB array for variable-sized pages
– 64-entry, 4-way set-associative TLB for 4-Kbyte pages
– 16-entry, fully-associative TLB array for variable-sized pages
– e500v1—A 256-entry, 2-way set-associative unified (for instruction and data accesses) L2
– e500v2—A 512-entry, 4-way set-associative unified (for instruction and data accesses) L2
Gbytes (2
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
CSRR1) and an rfci instruction
TLB array (TLB0) supports only 4-Kbyte pages
TLB array (TLB0) supports only 4-Kbyte pages
36
) on the e500v2
32
) of physical memory on the e500v1 and 64
32
) of effective address space
Core Complex Overview
5-9