MPC8544DS Freescale Semiconductor, MPC8544DS Datasheet - Page 366
![BOARD DEVELOPMENT SYSTEM 8544](/photos/37/58/375876/mpc8544e_sml.jpg)
MPC8544DS
Manufacturer Part Number
MPC8544DS
Description
BOARD DEVELOPMENT SYSTEM 8544
Manufacturer
Freescale Semiconductor
Series
PowerQUICC III™r
Type
MPUr
Datasheets
1.MPC8544VTALF.pdf
(117 pages)
2.MPC8544VTALF.pdf
(2 pages)
3.MPC8544VTALF.pdf
(1340 pages)
4.MPC8544DS.pdf
(2 pages)
Specifications of MPC8544DS
Contents
Board
Processor To Be Evaluated
MPC8544E
Data Bus Width
32 bit
Interface Type
Ethernet, I2C
Operating Supply Voltage
- 0.3 V to + 1.1 V
Leaded Process Compatible
Yes
Peak Reflow Compatible (260 C)
Yes
Rohs Compliant
Yes
For Use With/related Products
MPC8544
For Use With
PPC8544EVTANG - EVAL MPC8544 783FCPBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
- MPC8544VTALF PDF datasheet
- MPC8544VTALF PDF datasheet #2
- MPC8544VTALF PDF datasheet #3
- MPC8544DS PDF datasheet #4
- Current page: 366 of 1340
- Download datasheet (12Mb)
DDR Memory Controller
Read and write accesses to memory are burst oriented; accesses start at a selected location and continue
for a programmed number of higher locations (4 or 8) in a programmed sequence. Accesses to closed pages
start with the registration of an ACTIVE command followed by a READ or WRITE. (Accessing open
pages does not require an ACTIVE command.) The address bits registered coincident with the activate
command specifies the logical bank and row to be accessed. The address coincident with the READ or
WRITE command specify the logical bank and starting column for the burst access.
The data interface is source synchronous, meaning whatever sources the data also provides a clocking
signal to synchronize data reception. These bidirectional data strobes (MDQS[0:8]) are inputs to the
controller during reads and outputs during writes. The DDR SDRAM specification requires the data strobe
signals to be centered within the data tenure during writes and to be offset by the controller to the center
of the data tenure during reads. This delay is implemented in the controller for both reads and writes.
When ECC is enabled, 1 clock cycle is added to the read path to check ECC and correct single-bit errors.
ECC generation does not add a cycle to the write path.
9-42
Request from
Address from
Management
Data from
Data from
To Error
SDRAM
ECM
Master
Master
Master
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
DQ
Signals
Error
Address
Decode
RMW
Figure 9-33. DDR Memory Controller Block Diagram
ECC
DQ
Open
Table
Row
ECC
Delay Chain
DQ
FIFO
POS
FIFO
NEG
Address
SDRAM
Control
Control
SDRAM
Control
EN
EN
Freescale Semiconductor
DDR SDRAM
Memory Array
DDR SDRAM
Memory Control
Data Strobes
Data Signals
Clocks
Debug Signals
MA[15:0]
MCKE[0:3]
MODT[0:3]
MBA[2:0]
MSRCID[0:4]
MDVAL
MCS[0:3]
MCAS
MRAS
MWE
MDM[0:8]
MDQS[0:8]
MDQS[0:8]
MDQ[0:63]
MECC[0:7]
MCK[0:5]
MCK[0:5]
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