MPC8544DS Freescale Semiconductor, MPC8544DS Datasheet - Page 49
![BOARD DEVELOPMENT SYSTEM 8544](/photos/37/58/375876/mpc8544e_sml.jpg)
MPC8544DS
Manufacturer Part Number
MPC8544DS
Description
BOARD DEVELOPMENT SYSTEM 8544
Manufacturer
Freescale Semiconductor
Series
PowerQUICC III™r
Type
MPUr
Datasheets
1.MPC8544VTALF.pdf
(117 pages)
2.MPC8544VTALF.pdf
(2 pages)
3.MPC8544VTALF.pdf
(1340 pages)
4.MPC8544DS.pdf
(2 pages)
Specifications of MPC8544DS
Contents
Board
Processor To Be Evaluated
MPC8544E
Data Bus Width
32 bit
Interface Type
Ethernet, I2C
Operating Supply Voltage
- 0.3 V to + 1.1 V
Leaded Process Compatible
Yes
Peak Reflow Compatible (260 C)
Yes
Rohs Compliant
Yes
For Use With/related Products
MPC8544
For Use With
PPC8544EVTANG - EVAL MPC8544 783FCPBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
- MPC8544VTALF PDF datasheet
- MPC8544VTALF PDF datasheet #2
- MPC8544VTALF PDF datasheet #3
- MPC8544DS PDF datasheet #4
- Current page: 49 of 1340
- Download datasheet (12Mb)
Figure
Number
9-17
9-18
9-19
9-20
9-21
9-22
9-23
9-24
9-25
9-26
9-27
9-28
9-29
9-30
9-31
9-32
9-33
9-34
9-35
9-36
9-37
9-38
9-39
9-40
9-41
9-42
9-43
9-44
9-45
9-46
9-47
9-48
10-1
10-2
10-3
10-4
10-5
10-6
10-7
10-8
Freescale Semiconductor
DDR Initialization Extended Address Configuration Register
DDR IP Block Revision 1 (DDR_IP_REV1) ....................................................................... 9-32
DDR IP Block Revision 2 (DDR_IP_REV2) ....................................................................... 9-32
Memory Data Path Error Injection Mask High Register (DATA_ERR_INJECT_HI) ......... 9-33
Memory Data Path Error Injection Mask Low Register (DATA_ERR_INJECT_LO)......... 9-33
Memory Data Path Error Injection Mask ECC Register (ERR_INJECT)............................ 9-34
Memory Data Path Read Capture High Register (CAPTURE_DATA_HI).......................... 9-34
Memory Data Path Read Capture Low Register (CAPTURE_DATA_LO) ......................... 9-35
Memory Data Path Read Capture ECC Register (CAPTURE_ECC)................................... 9-35
Memory Error Detect Register (ERR_DETECT) ................................................................. 9-36
Memory Error Disable Register (ERR_DISABLE).............................................................. 9-36
Memory Error Interrupt Enable Register (ERR_INT_EN)................................................... 9-37
Memory Error Attributes Capture Register (CAPTURE_ATTRIBUTES)........................... 9-38
Memory Error Address Capture Register (CAPTURE_ADDRESS) ................................... 9-39
Memory Error Extended Address Capture Register (CAPTURE_EXT_ADDRESS).......... 9-40
Single-Bit ECC Memory Error Management Register (ERR_SBE) .................................... 9-40
DDR Memory Controller Block Diagram ............................................................................ 9-42
Typical Dual Data Rate SDRAM Internal Organization....................................................... 9-43
Typical DDR SDRAM Interface Signals .............................................................................. 9-43
Example 256-Mbyte DDR SDRAM Configuration With ECC ............................................ 9-44
DDR SDRAM Burst Read Timing—ACTTORW = 3, MCAS Latency = 2 ........................ 9-56
DDR SDRAM Single-Beat (Double Word) Write Timing—ACTTOR ............................... 9-56
DDR SDRAM Single-Beat (Double Word) Write Timing—ACTTORW = 3...................... 9-56
DDR SDRAM 4-Beat Burst Write Timing—ACTTORW = 4 ............................................. 9-57
DDR SDRAM Clock Distribution Example for x8 DDR SDRAMs .................................... 9-58
DDR SDRAM Mode-Set Command Timing ........................................................................ 9-58
Registered DDR SDRAM DIMM Burst Write Timing ........................................................ 9-59
Write Timing Adjustments Example for Write Latency = 1 ................................................. 9-60
DDR SDRAM Bank Staggered Auto Refresh Timing.......................................................... 9-61
DDR SDRAM Power-Down Mode ...................................................................................... 9-62
DDR SDRAM Self-Refresh Entry Timing ........................................................................... 9-63
DDR SDRAM Self-Refresh Exit Timing ............................................................................. 9-63
Interrupt Sources Block Diagram ......................................................................................... 10-2
Pass-Through Mode Example ............................................................................................... 10-5
Block Revision Register 1 (BRR1) ..................................................................................... 10-18
Block Revision Register 2 (BRR2) ..................................................................................... 10-19
Feature Reporting Register (FRR) ...................................................................................... 10-19
Global Configuration Register (GCR) ................................................................................ 10-20
Vendor Identification Register (VIR).................................................................................. 10-21
Processor Initialization Register (PIR) ............................................................................... 10-21
(DDR_INIT_EXT_ADDR).............................................................................................. 9-31
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Figures
Title
Number
Page
xlix
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