MPC8544DS Freescale Semiconductor, MPC8544DS Datasheet - Page 661
![BOARD DEVELOPMENT SYSTEM 8544](/photos/37/58/375876/mpc8544e_sml.jpg)
MPC8544DS
Manufacturer Part Number
MPC8544DS
Description
BOARD DEVELOPMENT SYSTEM 8544
Manufacturer
Freescale Semiconductor
Series
PowerQUICC III™r
Type
MPUr
Datasheets
1.MPC8544VTALF.pdf
(117 pages)
2.MPC8544VTALF.pdf
(2 pages)
3.MPC8544VTALF.pdf
(1340 pages)
4.MPC8544DS.pdf
(2 pages)
Specifications of MPC8544DS
Contents
Board
Processor To Be Evaluated
MPC8544E
Data Bus Width
32 bit
Interface Type
Ethernet, I2C
Operating Supply Voltage
- 0.3 V to + 1.1 V
Leaded Process Compatible
Yes
Peak Reflow Compatible (260 C)
Yes
Rohs Compliant
Yes
For Use With/related Products
MPC8544
For Use With
PPC8544EVTANG - EVAL MPC8544 783FCPBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
- MPC8544VTALF PDF datasheet
- MPC8544VTALF PDF datasheet #2
- MPC8544VTALF PDF datasheet #3
- MPC8544DS PDF datasheet #4
- Current page: 661 of 1340
- Download datasheet (12Mb)
When this attribute is asserted, the strobe is negated one quarter of a clock before the normal case. For
example, when ACS = 00 and CSNT = 1, LWEn is negated one quarter of a clock earlier, as shown in
Figure
14.4.2.2.3
ORx[TRLX] is provided for memory systems that require more relaxed timing between signals. Setting
TRLX = 1 has the following effect on timing:
Figure 14-26
Figure 14-27
consecutively.
Freescale Semiconductor
•
•
•
•
•
Figure 14-26. GPCM Relaxed Timing Read (XACS = 0, ACS = 1x, SCY = 1, EHTR = 0, TRLX = 1)
14-25.
An additional bus cycle is added between the address and control signals (but only if ACS ≠ 00).
The number of wait states specified by SCY is doubled, providing up to 30 wait states.
The extended hold time on read accesses (EHTR) is extended further.
LCSn signals are negated 1 cycle earlier during writes (but only if ACS ≠ 00).
LWE[0:3] signals are negated 1 cycle earlier during writes.
LBCTL
LCLK
LALE
LCS n
LAD
LOE
and
also shows address and data multiplexing on LAD[0:31] for a pair of writes issued
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
TA
A
Relaxed Timing
Figure 14-27
Address
ACS = 10
show relaxed timing read and write transactions. The example in
Latched Address
SCY = 1, TRLX = 1
ACS = 11
Read Data
Address
Local Bus Controller
14-41
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