MPC8544DS Freescale Semiconductor, MPC8544DS Datasheet - Page 15

• Manufacturer Part Number: MPC8544DS
• Description: BOARD DEVELOPMENT SYSTEM 8544
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8544DS

• Contents: Board
• Processor To Be Evaluated: MPC8544E
• Data Bus Width: 32 bit
• Interface Type: Ethernet, I2C
• Operating Supply Voltage: - 0.3 V to + 1.1 V
• Leaded Process Compatible: Yes
• Peak Reflow Compatible (260 C): Yes
• Rohs Compliant: Yes
• For Use With/related Products: MPC8544
• For Use With: PPC8544EVTANG - EVAL MPC8544 783FCPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Paragraph
Number
9.5.7
9.5.8
9.5.8.1
9.5.8.2
9.5.8.2.1
9.5.9
9.5.10
9.5.11
9.5.12
9.6
9.6.1
9.6.2
9.6.3
9.6.3.1
9.6.3.2
9.6.3.3
10.1
10.1.1
10.1.2
10.1.3
10.1.4
10.1.4.1
10.1.4.2
10.1.5
10.1.5.1
10.1.5.2
10.2
10.2.1
10.2.2
10.3
10.3.1
10.3.1.1
10.3.1.2
10.3.1.3
10.3.1.4
10.3.1.5
Freescale Semiconductor
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Initialization/Application Information ........................................................................... 9-68
Introduction.................................................................................................................... 10-1
External Signal Descriptions ......................................................................................... 10-7
Memory Map/Register Definition ................................................................................. 10-9
DDR SDRAM Write Timing Adjustments ................................................................ 9-59
DDR SDRAM Refresh .............................................................................................. 9-60
DDR Data Beat Ordering........................................................................................... 9-64
Page Mode and Logical Bank Retention ................................................................... 9-64
Error Checking and Correcting (ECC) ...................................................................... 9-65
Error Management ..................................................................................................... 9-67
Programming Differences Between Memory Types.................................................. 9-69
DDR SDRAM Initialization Sequence ...................................................................... 9-72
Using Forced Self-Refresh Mode to Implement a Battery-Backed
Overview.................................................................................................................... 10-1
Features...................................................................................................................... 10-3
Interrupts to the Processor Core................................................................................. 10-3
Modes of Operation ................................................................................................... 10-4
Interrupt Sources........................................................................................................ 10-5
Signal Overview ........................................................................................................ 10-7
Detailed Signal Descriptions ..................................................................................... 10-8
Global Registers....................................................................................................... 10-18
DDR SDRAM Refresh Timing.............................................................................. 9-61
DDR SDRAM Refresh and Power-Saving Modes ................................................ 9-61
RAM System ......................................................................................................... 9-72
Hardware Based Self-Refresh................................................................................ 9-72
Software Based Self-Refresh................................................................................. 9-73
Bypassing Re-initialization During Battery-Backed Operation ............................ 9-73
Mixed Mode (GCR[M] = 1) .................................................................................. 10-4
Pass-Through Mode (GCR[M] = 0) ...................................................................... 10-5
Interrupt Routing—Mixed Mode........................................................................... 10-6
Internal Interrupt Sources ...................................................................................... 10-6
Block Revision Register 1 (BRR1)...................................................................... 10-18
Block Revision Register 2 (BRR2)...................................................................... 10-19
Feature Reporting Register (FRR)....................................................................... 10-19
Global Configuration Register (GCR)................................................................. 10-20
Vendor Identification Register (VIR) .................................................................. 10-21
Self-Refresh in Sleep Mode............................................................................... 9-63
Programmable Interrupt Controller
Contents
Chapter 10
Title
Number
Page
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