MPC8544DS Freescale Semiconductor, MPC8544DS Datasheet - Page 319
MPC8544DS
Manufacturer Part Number
MPC8544DS
Description
BOARD DEVELOPMENT SYSTEM 8544
Manufacturer
Freescale Semiconductor
Series
PowerQUICC III™r
Type
MPUr
Datasheets
1.MPC8544VTALF.pdf
(117 pages)
2.MPC8544VTALF.pdf
(2 pages)
3.MPC8544VTALF.pdf
(1340 pages)
4.MPC8544DS.pdf
(2 pages)
Specifications of MPC8544DS
Contents
Board
Processor To Be Evaluated
MPC8544E
Data Bus Width
32 bit
Interface Type
Ethernet, I2C
Operating Supply Voltage
- 0.3 V to + 1.1 V
Leaded Process Compatible
Yes
Peak Reflow Compatible (260 C)
Yes
Rohs Compliant
Yes
For Use With/related Products
MPC8544
For Use With
PPC8544EVTANG - EVAL MPC8544 783FCPBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
- MPC8544VTALF PDF datasheet
- MPC8544VTALF PDF datasheet #2
- MPC8544VTALF PDF datasheet #3
- MPC8544DS PDF datasheet #4
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- Download datasheet (12Mb)
8.2.1.6
The ECM error enable register (EEER) shown in
the e500 core through the internal int interrupt signal.
Table 8-7
8.2.1.7
The ECM error attributes capture register (EEATR) is shown in
Table 8-8
Freescale Semiconductor
Offset 0x0_1E08
Reset
0–30
Offset 0x0_1E0C
Reset
8–10
Bits Name
Bits
0–2
3–7
31
W
R
W
R
0
LAEE Local access error enable. Note that a read that attempts to access an unmapped target causes the
0
describes EEER fields.
describes EEATR fields.
BYTE_CNT Byte count. Specifies the transaction byte count.
—
—
Name
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
—
—
2 3
ECM Error Enable Register (EEER)
ECM Error Attributes Capture Register (EEATR)
Reserved
assertion of core_fault_in , which causes the core to generate a machine check interrupt, unless it is
disabled (by clearing HID1[RFXE]). If HID1[RFXE] is zero and this error occurs, LAEE must be set to
ensure that an interrupt is generated. For more information, see
Implementation-Dependent Register 1 (HID1).”
0 Disable reporting local access errors as interrupts.
1 Enable reporting local access errors as interrupts.
BYTE_CNT
Reserved
00000 32 bytes
00001 1 byte
00010 2 bytes
Reserved
Figure 8-8. ECM Error Attributes Capture Register (EEATR)
7 8
Figure 8-7. ECM Error Enable Register (EEER)
—
Table 8-8. EEATR Field Descriptions
Table 8-7. EEER Field Descriptions
10 11
SRC_ID
Figure 8-7
15 16 17
—
All zeros
All zeros
Description
—
Description
TTYPE
enables the reporting of error conditions to
00100 4 bytes
01000 8 bytes
10000 16 bytes
Figure
20 21
Section 6.10.2, “Hardware
8-8.
—
Access: Read Only
e500 Coherency Module
Access: Read/Write
30
30
LAEE
VAL
31
31
8-7
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