MPC8544DS Freescale Semiconductor, MPC8544DS Datasheet - Page 241

• Manufacturer Part Number: MPC8544DS
• Description: BOARD DEVELOPMENT SYSTEM 8544
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8544DS

• Contents: Board
• Processor To Be Evaluated: MPC8544E
• Data Bus Width: 32 bit
• Interface Type: Ethernet, I2C
• Operating Supply Voltage: - 0.3 V to + 1.1 V
• Leaded Process Compatible: Yes
• Peak Reflow Compatible (260 C): Yes
• Rohs Compliant: Yes
• For Use With/related Products: MPC8544
• For Use With: PPC8544EVTANG - EVAL MPC8544 783FCPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

6.9
6.9.1
6.9.2
Freescale Semiconductor
Reset
Reset
32–61
62–63
32–61
SPR 513
SPR 514
Bits
Bits
62
63
W
R
W
R
32
32
target address
entry address
Branch buffer
Branch buffer
Branch Target Buffer (BTB) Registers
IAB[0–1]
BDIRPR
Name
Name
IAB2
Branch Buffer Entry Address Register (BBEAR)
Branch Buffer Target Address Register (BBTAR)
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Figure 6-30. Branch Buffer Target Address Register (BBTAR)
Figure 6-29. Branch Buffer Entry Address Register (BBEAR)
Branch buffer entry effective address bits 0–29
Instruction after branch (with BBTAR[62]). 3-bit pointer that points to the instruction in the cache line
after the branch. See the description in the bblels instruction in the EREF. If the branch is the last
instruction in the cache block, IAB = 000, to indicate the next sequential instruction, which resides in
the zeroth position of the next cache block.
Branch buffer target effective address bits 0–29
Instruction after branch bit 2 (with BBEAR[62–63]). IAB is a 3-bit pointer that points to the instruction
in the cache line after the branch. See the description for bblels in the EREF. If the branch is the last
instruction in the cache block, IAB = 000, to indicate the next sequential instruction, which resides in
the zeroth position of the next cache block.
Branch direction prediction. The user can pick the direction of the predicted branch.
0 The locked address is always predicted as not taken.
1 The locked address is always predicted as taken.
Table 6-15. BBEAR Field Descriptions
Table 6-16. BBTAR Field Descriptions
Branch buffer target address
Branch buffer entry address
All zeros
All zeros
Description
Description
Access: User read/write
Access: User read/write
Core Register Summary
61
IAB2 BDIRPR
62
61
IAB[0–1]
62
63
6-23
63