MPC8544DS Freescale Semiconductor, MPC8544DS Datasheet - Page 9

• Manufacturer Part Number: MPC8544DS
• Description: BOARD DEVELOPMENT SYSTEM 8544
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8544DS

• Contents: Board
• Processor To Be Evaluated: MPC8544E
• Data Bus Width: 32 bit
• Interface Type: Ethernet, I2C
• Operating Supply Voltage: - 0.3 V to + 1.1 V
• Leaded Process Compatible: Yes
• Peak Reflow Compatible (260 C): Yes
• Rohs Compliant: Yes
• For Use With/related Products: MPC8544
• For Use With: PPC8544EVTANG - EVAL MPC8544 783FCPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

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Number
5.9.4
5.10
5.10.1
5.10.2
5.10.3
5.10.4
5.11
5.12
5.12.1
5.12.2
5.12.3
5.13
5.13.1
5.13.1.1
5.13.1.2
5.13.2
5.13.3
5.13.4
5.13.5
5.13.6
5.14
6.1
6.1.1
6.2
6.2.1
6.3
6.3.1
6.3.2
6.4
6.4.1
6.4.2
6.4.3
6.5
6.5.1
6.5.2
6.5.3
6.5.4
Freescale Semiconductor
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Memory Coherency ....................................................................................................... 5-26
Core Complex Bus (CCB) ............................................................................................. 5-27
Performance Monitoring................................................................................................ 5-28
Legacy Support of Power Architecture Technology...................................................... 5-29
PowerQUICC III Implementation Details ..................................................................... 5-31
Overview.......................................................................................................................... 6-1
Register Model for 32-Bit Implementations .................................................................... 6-3
Registers for Computational Operations.......................................................................... 6-8
Registers for Branch Operations...................................................................................... 6-9
Processor Control Registers........................................................................................... 6-11
TLB Coherency.......................................................................................................... 5-26
Atomic Update Memory References ......................................................................... 5-26
Memory Access Ordering.......................................................................................... 5-27
Cache Control Instructions ........................................................................................ 5-27
Programmable Page Characteristics .......................................................................... 5-27
Global Control Register ............................................................................................. 5-28
Performance Monitor Counter Registers ................................................................... 5-28
Local Control Registers ............................................................................................. 5-28
Instruction Set Compatibility..................................................................................... 5-29
Memory Subsystem ................................................................................................... 5-30
Exception Handling ................................................................................................... 5-30
Memory Management................................................................................................ 5-30
Reset........................................................................................................................... 5-30
Little-Endian Mode.................................................................................................... 5-31
Register Set .................................................................................................................. 6-1
Special-Purpose Registers (SPRs) ............................................................................... 6-4
General-Purpose Registers (GPRs).............................................................................. 6-8
Integer Exception Register (XER)............................................................................... 6-8
Condition Register (CR) .............................................................................................. 6-9
Link Register (LR)..................................................................................................... 6-11
Count Register (CTR)................................................................................................ 6-11
Machine State Register (MSR) .................................................................................. 6-11
Processor ID Register (PIR) ...................................................................................... 6-13
Processor Version Register (PVR)............................................................................. 6-13
System Version Register (SVR)................................................................................. 6-14
User Instruction Set ............................................................................................... 5-29
Supervisor Instruction Set...................................................................................... 5-29
Core Register Summary
Contents
Chapter 6
Title
Number
Page
ix