MPC8544DS Freescale Semiconductor, MPC8544DS Datasheet - Page 30

• Manufacturer Part Number: MPC8544DS
• Description: BOARD DEVELOPMENT SYSTEM 8544
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8544DS

• Contents: Board
• Processor To Be Evaluated: MPC8544E
• Data Bus Width: 32 bit
• Interface Type: Ethernet, I2C
• Operating Supply Voltage: - 0.3 V to + 1.1 V
• Leaded Process Compatible: Yes
• Peak Reflow Compatible (260 C): Yes
• Rohs Compliant: Yes
• For Use With/related Products: MPC8544
• For Use With: PPC8544EVTANG - EVAL MPC8544 783FCPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Paragraph
Number
15.5.3.7
15.5.3.7.1
15.5.3.7.2
15.5.3.8
15.5.3.8.1
15.5.3.9
15.5.3.9.1
15.5.3.9.2
15.5.3.10
15.5.3.10.1
15.5.3.10.2
15.5.4
15.5.4.1
15.5.4.1.1
15.5.4.1.2
15.5.4.1.3
15.5.4.2
15.5.4.2.1
15.5.4.2.2
15.5.4.3
15.5.4.3.1
15.5.4.3.2
15.5.4.3.3
15.5.4.3.4
15.5.4.3.5
15.5.4.3.6
15.5.4.3.7
15.5.4.3.8
15.5.4.3.9
15.5.4.3.10
15.6
15.6.1
15.6.1.1
15.6.1.2
15.6.1.3
15.6.1.4
15.6.1.5
15.6.1.6
15.6.1.7
15.6.2
xxx
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Functional Description............................................................................................... 15-127
Ten-Bit Interface (TBI) .......................................................................................... 15-115
Connecting to Physical Interfaces on Ethernet ...................................................... 15-127
Connecting to FIFO Interfaces .............................................................................. 15-137
Hash Function Registers .................................................................................... 15-108
FIFO Registers................................................................................................... 15-110
DMA Attribute Registers....................................................................................15-111
Lossless Flow Control Configuration Registers ................................................ 15-113
TBI Transmit Process ........................................................................................ 15-115
TBI Receive Process.......................................................................................... 15-116
TBI MII Set Register Descriptions .................................................................... 15-116
Media-Independent Interface (MII) ................................................................... 15-128
Reduced Media-Independent Interface (RMII) ................................................. 15-128
Gigabit Media-Independent Interface (GMII) ................................................... 15-129
Reduced Gigabit Media-Independent Interface (RGMII) ................................. 15-129
Ten-Bit Interface (TBI)...................................................................................... 15-131
Reduced Ten-Bit Interface (RTBI) .................................................................... 15-132
Ethernet Physical Interfaces Signal Summary................................................... 15-133
Individual/Group Address Registers 0–7 (IGADDRn) ................................. 15-108
Group Address Registers 0–7 (GADDRn) .................................................... 15-109
FIFO Configuration Register (FIFOCFG)..................................................... 15-110
Attribute Register (ATTR)..............................................................................15-111
Attribute Extract Length and Extract Index Register (ATTRELI) ............... 15-112
Receive Queue Parameters 0–7 (RQPRM0–PQPRM7) ................................ 15-113
Receive Free Buffer Descriptor Pointer Registers 0–7
Packet Encapsulation..................................................................................... 15-115
8B10B Encoding............................................................................................ 15-115
Preamble Shortening...................................................................................... 15-115
Synchronization ............................................................................................. 15-116
Auto-Negotiation for 1000BASE-X.............................................................. 15-116
Control Register (CR).................................................................................... 15-117
Status Register (SR)....................................................................................... 15-118
AN Advertisement Register (ANA) .............................................................. 15-119
AN Link Partner Base Page Ability Register (ANLPBPA)........................... 15-121
AN Expansion Register (ANEX) .................................................................. 15-122
AN Next Page Transmit Register (ANNPT).................................................. 15-123
AN Link Partner Ability Next Page Register (ANLPANP) .......................... 15-124
Extended Status Register (EXST) ................................................................. 15-124
Jitter Diagnostics Register (JD) ..................................................................... 15-125
TBI Control Register (TBICON)................................................................... 15-126
(RFBPTR0–RFBPTR7) ............................................................................. 15-114
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