MPC8544DS Freescale Semiconductor, MPC8544DS Datasheet - Page 279

• Manufacturer Part Number: MPC8544DS
• Description: BOARD DEVELOPMENT SYSTEM 8544
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8544DS

• Contents: Board
• Processor To Be Evaluated: MPC8544E
• Data Bus Width: 32 bit
• Interface Type: Ethernet, I2C
• Operating Supply Voltage: - 0.3 V to + 1.1 V
• Leaded Process Compatible: Yes
• Peak Reflow Compatible (260 C): Yes
• Rohs Compliant: Yes
• For Use With/related Products: MPC8544
• For Use With: PPC8544EVTANG - EVAL MPC8544 783FCPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Freescale Semiconductor
0x2_0E4C L2ERRATTR—L2 error attributes capture register
0x2_010C
0x2_0E00
0x2_0E04
0x2_0E08
0x2_0E20
0x2_0E24
0x2_0E28
0x2_0E40
0x2_0E44
0x2_0E48
0x2_0E50
0x2_0E54
0x2_0E58
0x2_0000
0x2_0010
0x2_0014
0x2_0018
0x2_0020
0x2_0024
0x2_0028
0x2_0030
0x2_0034
0x2_0038
0x2_0040
0x2_0044
0x2_0048
0x2_0100
0x2_0104
0x2_0108
Offset
L2CTL—L2 control register
L2CEWAR0—L2 cache external write address register 0
L2CEWAREA0—L2 cache external write address register extended
address 0
L2CEWCR0—L2 cache external write control register 0
L2CEWAR1—L2 cache external write address register 1
L2CEWAREA1—L2 cache external write address register extended
address 1
L2CEWCR1—L2 cache external write control register 1
L2CEWAR2—L2 cache external write address register 2
L2CEWAREA2—L2 cache external write address register extended
address 2
L2CEWCR2—L2 cache external write control register 2
L2CEWAR3—L2 cache external write address register 3
L2CEWAREA3—L2 cache external write address register extended
address 3
L2CEWCR3—L2 cache external write control register 3
L2SRBAR0—L2 memory-mapped SRAM base address register 0
L2SRBAREA0—L2 memory-mapped SRAM base address register
extended address 0
L2SRBAR1—L2 memory-mapped SRAM base address register 1
L2SRBAREA1—L2 memory-mapped SRAM base address register
extended address 1
L2ERRINJHI—L2 error injection mask high register
L2ERRINJLO—L2 error injection mask low register
L2ERRINJCTL—L2 error injection tag/ECC control register
L2CAPTDATAHI—L2 error data high capture register
L2CAPTDATALO—L2 error data low capture register
L2CAPTECC—L2 error syndrome register
L2ERRDET—L2 error detect register
L2ERRDIS—L2 error disable register
L2ERRINTEN—L2 error interrupt enable register
L2ERRADDRH—L2 error address capture register high
L2ERRADDRL—L2 error address capture register low
L2ERRCTL—L2 error control register
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Table 7-3. L2/SRAM Memory-Mapped Registers
Register
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
w1c
R
R
R
R
R
0x2000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
Reset
L2 Look-Aside Cache/SRAM
Section/Page
7.3.1.2.1/7-13
7.3.1.2.2/7-14
7.3.1.2.3/7-14
7.3.1.2.1/7-13
7.3.1.2.2/7-14
7.3.1.2.3/7-14
7.3.1.2.1/7-13
7.3.1.2.2/7-14
7.3.1.2.3/7-14
7.3.1.2.1/7-13
7.3.1.2.2/7-14
7.3.1.2.3/7-14
7.3.1.3.1/7-16
7.3.1.3.2/7-17
7.3.1.3.1/7-16
7.3.1.3.2/7-17
7.3.1.4.1/7-18
7.3.1.4.1/7-18
7.3.1.4.1/7-18
7.3.1.4.2/7-20
7.3.1.4.2/7-20
7.3.1.4.2/7-20
7.3.1.4.2/7-20
7.3.1.4.2/7-20
7.3.1.4.2/7-20
7.3.1.4.2/7-20
7.3.1.4.2/7-20
7.3.1.4.2/7-20
7.3.1.4.2/7-20
7.3.1.1/7-10
7-9