MPC8544DS Freescale Semiconductor, MPC8544DS Datasheet - Page 700
MPC8544DS
Manufacturer Part Number
MPC8544DS
Description
BOARD DEVELOPMENT SYSTEM 8544
Manufacturer
Freescale Semiconductor
Series
PowerQUICC III™r
Type
MPUr
Datasheets
1.MPC8544VTALF.pdf
(117 pages)
2.MPC8544VTALF.pdf
(2 pages)
3.MPC8544VTALF.pdf
(1340 pages)
4.MPC8544DS.pdf
(2 pages)
Specifications of MPC8544DS
Contents
Board
Processor To Be Evaluated
MPC8544E
Data Bus Width
32 bit
Interface Type
Ethernet, I2C
Operating Supply Voltage
- 0.3 V to + 1.1 V
Leaded Process Compatible
Yes
Peak Reflow Compatible (260 C)
Yes
Rohs Compliant
Yes
For Use With/related Products
MPC8544
For Use With
PPC8544EVTANG - EVAL MPC8544 783FCPBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
- MPC8544VTALF PDF datasheet
- MPC8544VTALF PDF datasheet #2
- MPC8544VTALF PDF datasheet #3
- MPC8544DS PDF datasheet #4
- Current page: 700 of 1340
- Download datasheet (12Mb)
Local Bus Controller
14.5.1.2
To achieve high bus speed interfaces for synchronous SRAMs or SDRAMs, a hierarchy of the
memories/peripherals connected to the local bus is suggested, as shown in
The multiplexed address/data bus sees the capacitive loading of the data signals of the fast SDRAMs or
synchronous SRAMs plus one load for an address latch plus one load for a buffer to the slow memories.
The loadings of all other memories and peripherals are hidden behind the buffer and the latch. The system
designer needs to investigate the loading scenario and ensure that I/O timings can be met with the loading
determined by the connected components.
14.5.1.3
To achieve the highest possible bus speeds on the local bus, it is recommended to reduce the number of
devices connected directly to the local bus even further. For those cases probably only one bank of
synchronous SRAMs or SDRAMs should be used and instead of using a separate latch and a separate bus
transceiver, a bus demultiplexer combining those two functions into one device should be used.
14-80
Local Bus Interface
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Peripheral Hierarchy on the Local Bus
Peripheral Hierarchy on the Local Bus for Very High Bus Speeds
LAD[0:31]
LA[27:31]
LBCTL
LALE
Figure 14-69. Local Bus Peripheral Hierarchy
Muxed Address/Data
Non-Muxed Address
Buffered Data
DIR
A
D
LE
Latch
Buffer
Q
B
A
DQ
MA
Peripherals
Figure
Memories
Slower
and
14-69.
A
DQ
A
DQ
SDRAM
SSRAM
Freescale Semiconductor
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