MPC8544DS Freescale Semiconductor, MPC8544DS Datasheet - Page 780
![BOARD DEVELOPMENT SYSTEM 8544](/photos/37/58/375876/mpc8544e_sml.jpg)
MPC8544DS
Manufacturer Part Number
MPC8544DS
Description
BOARD DEVELOPMENT SYSTEM 8544
Manufacturer
Freescale Semiconductor
Series
PowerQUICC III™r
Type
MPUr
Datasheets
1.MPC8544VTALF.pdf
(117 pages)
2.MPC8544VTALF.pdf
(2 pages)
3.MPC8544VTALF.pdf
(1340 pages)
4.MPC8544DS.pdf
(2 pages)
Specifications of MPC8544DS
Contents
Board
Processor To Be Evaluated
MPC8544E
Data Bus Width
32 bit
Interface Type
Ethernet, I2C
Operating Supply Voltage
- 0.3 V to + 1.1 V
Leaded Process Compatible
Yes
Peak Reflow Compatible (260 C)
Yes
Rohs Compliant
Yes
For Use With/related Products
MPC8544
For Use With
PPC8544EVTANG - EVAL MPC8544 783FCPBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
- MPC8544VTALF PDF datasheet
- MPC8544VTALF PDF datasheet #2
- MPC8544VTALF PDF datasheet #3
- MPC8544DS PDF datasheet #4
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- Download datasheet (12Mb)
Enhanced Three-Speed Ethernet Controllers
TRANSMIT command is issued and the frame completes its transmission) in order to change the next
TxBD eTSEC transmits.
Table 15-23
15.5.3.2.10 Transmit Descriptor Base Address High Register (TBASEH)
The TBASEH register is written by the user with the most significant address bits common to all TxBD
addresses, including TBASE0–TBASE7 and TBPTR0–TBPTR7. As a consequence, all TxBD rings must
be placed in a 4 Gbyte segment of memory whose base address is prefixed by the bits in TBASEH. Data
buffers are located in a potentially different region, based at TBDBPH.
TBASEH register.
Table 15-24
15-48
29–31
28–31 TBASEH Most significant bits common to all TxBD addresses—except data buffer pointers. The user must initialize
0–28
0–27
Bits
Bits
Offset eTSEC1:0x2_4184+8× n ; eTSEC3:0x2_5184+8× n
Reset
Offset eTSEC1:0x2_4200; eTSEC3:0x2_5200
Reset
W
W
R
R
TBPTR n Current TxBD pointer for TxBD ring n . Points to the current BD being processed or to the next BD the
Name
Name
0
0
—
—
describes the fields of the TBPTRn register.
describes the fields of the TBASEH register.
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
transmitter uses when it is idling. When the end of the TxBD ring is reached, eTSEC initializes TBPTR n to
the value in the corresponding TBASE n . The TBPTR register is internally written by the eTSEC’s DMA
controller during transmission. The pointer increments by eight (bytes) each time a descriptor is closed
successfully by the eTSEC. Note that the three least significant bits of this register are read-only and zero.
After an error condition, the eTSEC returns TBPTR n to point to the first BD of the frame partially transmitted.
Reserved
Reserved
TBASEH before enabling the eTSEC transmit function.
Figure 15-19. TBPTR0–TBPTR7 Register Definition
Figure 15-20. TBASEH Register Definition
Table 15-24. TBASEH Field Descriptions
Table 15-23. TBPTR n Field Descriptions
TBPTR n
—
All zeros
All zeros
Description
Description
Figure 15-20
Freescale Semiconductor
describes the
Access: Read/Write
Access: Read/Write
27 28
28 29
TBASEH
—
31
31
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