MPC8544DS Freescale Semiconductor, MPC8544DS Datasheet - Page 849

• Manufacturer Part Number: MPC8544DS
• Description: BOARD DEVELOPMENT SYSTEM 8544
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8544DS

• Contents: Board
• Processor To Be Evaluated: MPC8544E
• Data Bus Width: 32 bit
• Interface Type: Ethernet, I2C
• Operating Supply Voltage: - 0.3 V to + 1.1 V
• Leaded Process Compatible: Yes
• Peak Reflow Compatible (260 C): Yes
• Rohs Compliant: Yes
• For Use With/related Products: MPC8544
• For Use With: PPC8544EVTANG - EVAL MPC8544 783FCPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

15.5.4.3.1
Figure 15-107
Table 15-111
Freescale Semiconductor
Offset 0x00
Reset
Bits
4–5
0
1
2
3
W
R PHY
Reset
PHY Reset PHY reset. This bit is cleared by default. This bit is self-clearing.
1
Speed[0] Speed selection. This bit defaults to a cleared state and should always be cleared, which corresponds to
0
0
Enable
Name
0x02–0x03
R = means Read-only, WO = Write Only, R/W = Read and Write, LH = Latches High, LL = Latches Low,
SC = Self-clearing,
AN
Address
—
—
Offset
0x0F
0x01
0x04
0x05
0x06
0x07
0x08
0x10
0x11
— Speed[0] AN Enable
0
1
describes the fields of the CR register.
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
describes the definition for the CR register.
Control Register (CR)
0 Normal operation.
1 The internal state of the TBI is reset. This in turn may change the state of the TBI link partner.
Reserved
1000 Mbps speed.Setting this field controls the speed at which the TBI operates. The table for Speed[1]
provides the appropriate encoding. Its default is bit[2] = ‘0’; bit[9] = ’1’.
Auto-negotiation enable. This bit is set by default.
0 The values programmed in bits 2, 7 and 9 determine the operating condition of the link.
1 Auto-negotiation process enabled.
Reserved
0
2
Status (SR)
Reserved
AN advertisement (ANA)
AN link partner base page ability
(ANLPBPA)
AN expansion (ANEX)
AN next page transmit (ANNPT)
AN link partner ability next page
(ANLPANP)
Extended status (EXST)
Jitter diagnostics (JD)
TBI control (TBICON)
3
1
Table 15-110. TBI MII Register Set (continued)
Figure 15-107. Control Register Definition
Table 15-111. CR Field Descriptions
0
4
Name
—
0
5
Reset AN Full Duplex — Speed[1]
0
6
Description
1
7
R, LH, LL
Access
R/W, R
RW, R
R, LH
R/W
R/W
R
R
R
R
8
0
1
9
Enhanced Three-Speed Ethernet Controllers
2 bytes
16 bits
16 bits
16 bits
16 bits
16 bits
16 bits
16 bits
16 bits
16 bits
Size
10
0
15.5.4.3.10/15-126
0
15.5.4.3.2/15-118
15.5.4.3.2/15-118
15.5.4.3.4/15-121
15.5.4.3.5/15-122
15.5.4.3.6/15-123
15.5.4.3.7/15-124
15.5.4.3.8/15-124
15.5.4.3.9/15-125
Section/page
0
—
Access: Read/Write
—
0
0
15-117
15
0